Static memory memory point and application to an image sensor

Abstract

The invention relates to a memory point of SRAM (static memory) type memory. The memory point conventionally comprises two inverters mounted head-to-tail between two nodes, and at least one access transistor able to be made conductive during a writing phase and linked between a first node and a line of data to be written, characterized in that it comprises an isolating transistor inserted in series between the output of a first inverter and the first node, the isolating transistor being controlled by an insulation signal at the start of a writing phase. The current consumption is reduced when the state of the memory point has to be inverted.

1 . Memory point of a static memory SRAM, comprising two inverters mounted head-to-tail between two nodes and having their inputs connected to theses nodes, and at least one access transistor able to be made conductive during a writing phase and linked between a first node and a line of data to be written, said memory point comprising an isolating transistor inserted in series between the output of a first inverter and the first node, the isolating transistor (TAB) being controlled by an isolation signal at the start of a writing phase. 
   
   
       2 . Memory point according to  claim 1 , wherein the access transistor and the isolating transistor are controlled in phase opposition by one and the same write control line which makes the access transistor conductive while it blocks the isolating transistor and vice versa. 
   
   
       3 . Memory point according to  claim 1 , comprising a second line of data to be written conveying binary information complementing that of the first line of data, with an access transistor between each line of data and a respective node, a respective isolating transistor being provided between the output of each inverter and a corresponding node. 
   
   
       4 . Memory point according to  claim 1 , comprising a line of data to be read distinct from the line of data to be written, a read transistor being provided in the memory point, controlled by the second node, and an access transistor being provided, controlled by a read control line, to link the read transistor to the line of data to be read. 
   
   
       5 . Memory point according to  claim 4 , wherein an additional inverter is inserted between the data write line and the corresponding access transistor. 
   
   
       6 . CMOS image sensor comprising a matrix of photosensitive pixels arranged in N lines and P columns, an analogue-digital converter linked to a column conductor and able to supply a word of M bits representing the signal obtained from a pixel of the column, and at least one memory M*P memory points, able to receive and store P words obtained from the analogue-digital conversion and corresponding to P pixels of a line, and to then restore these P words on a read command, characterized in that each memory point is constructed according to  claim 1 . 
   
   
       7 . Image sensor according to  claim 6 , comprising two memories of M*P memory points operating alternately, one in write mode and the other in read mode. 
   
   
       8 . Memory point according to  claim 2 , comprising a line of data to be read distinct from the line of data to be written, a read transistor being provided in the memory point, controlled by the second node, and an access transistor being provided, controlled by a read control line, to link the read transistor to the line of data to be read. 
   
   
       9 . Memory point according to  claim 8 , wherein an additional inverter is inserted between the data write line and the corresponding access transistor.