Rotary clock flash analog to digital converter system and method

Abstract

System and method for converting an analog voltage to a digital signal. The system includes an input voltage sampler, a ramp generator, a comparator, a time-to-digital converter (TDC), and a multiphase oscillator, preferably a rotary traveling wave oscillator, that provides the critical system timing. The phases of the multiphase oscillator define a sampling interval during which the input voltage is sampled and held and a conversion interval during which the ramp generator, comparator, and TDC operate to convert the sampled voltage to the digital signal. The TDC samples at times provided by the phases of the multiphase oscillator to form the bits of the digital signal. The sampler, ramp generator, and comparator can be constructed from multiple fragments, one of which is selectable for calibration while the rest of the fragments are joined for normal operation. Multiple converters can be interleaved to increase the sampling rate.

1 . A sample and hold circuit comprising:
 an input attenuator connected between an input signal to be sampled and a first reference voltage and having first and second attenuated signal output;   a capacitor for holding a sampled signal and having one electrode connected to the first reference voltage;   a sampling transistor having a gate, source and drain and a channel defined between the source and drain, the channel of the sampling transistor being connected between the second signal output of the input attenuator and the other electrode of holding capacitor;   a precharge/discharge circuit connected between the first and second supply voltages, and having an output connected to the gate of the sampling transistor and an input connected to a signal defining a sampling interval, the precharge/discharge circuit pulling the gate of the sampling transistor towards a second supply voltage during the sampling interval and discharging the gate of the sampling transistor to the first supply voltage otherwise; and   a source follower circuit having an enable input connected to enabling signal that is activated slightly before the beginning of the sampling interval and deactivated slightly before the end of the sampling interval, the source follower circuit being connected between the first signal output of the input attenuator and the gate of the sampling transistor so that the gate of the sampling transistor follows the voltage of the first output when the source follower circuit is enabled.   
     
     
         2 . A sample and hold circuit as recited in  claim 1 , wherein the input attenuator includes first, second and third resistors connected in series between the input signal to be sampled and the first reference voltage, a junction between the first and second resistors providing the first attenuated signal output, a junction between the second and third resistors providing the second attenuated signal output. 
     
     
         3 . A sample and hold circuit as recited in  claim 1 , wherein the precharge/discharge circuit includes an NMOS transistor and a PMOS transistor, each having a gate, source and drain and a channel defined between the source and drain, the gates of the NMOS transistor and the PMOS transistor being connected to the interval signal, the channels being connected together at the gate of the sampling transistor and being connected in series between the first and second supply voltages. 
     
     
         4 . A sample and hold circuit as recited in  claim 1 , wherein the precharge/discharge circuit includes an NMOS transistor and a resistor, the NMOS transistor having a gate, source and drain and a channel defined between the source and drain, the gate of the NMOS transistor being connected to the interval signal, the channel and resistor being connected together at the gate of the sampling transistor and being connected in series between the first and second supply voltages. 
     
     
         5 . A sample and hold circuit as recited in  claim 1 , wherein the source follower circuit includes an NMOS transistor and a PMOS transistor, each having a gate, source and drain and a channel defined between the source and drain, the channels being connected in series between the first supply voltage of the first transistor and the gate of the sampling transistor, the gate of the NMOS transistor being connected to the enabling signal, and the gate of the PMOS transistor being connected to the first signal output of the input attenuator.