Data processing device and method

Abstract

A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed.

1 . A data processing device comprising:
 a multidimensional array of data processing coarse grained logic elements (PAEs) that are operated at a first clock rate and that communicate with one another and/or other elements via busses and/or communication lines operated at a second clock rate,   wherein:
 the first clock rate is higher than the second; 
 the coarse grained logic elements comprise storage means for storing data needed to be processed; 
 the array is controlled to perform data-flow data processing; 
 the data storage means is adapted for storage of operands and/or intermediate results; and 
 a valid bit is provided for each entry of the storage means. 
   
     
     
         2 . A data processing device according to  claim 1 , wherein the device is adapted for data processing of a coarse grained logic element of the array to be effected in response to all valid bits of needed data and/or triggers being valid. 
     
     
         3 . A data processing device according to  claim 1 , wherein;
 the data-flow processing has a main data flow direction;   said coarse grained logic elements include at least one coarse grained hardware logic element adapted to effect data processing while allowing data to flow in said main data flow direction.   
     
     
         4 . A data processing device according to  claim 3 , wherein the at least one coarse grained logic element includes a coarse grained logic element that includes first ALU having an upstream input side and a data downstream output side and a second ALU that provides for data flow in a direction reverse from that of the first ALU. 
     
     
         5 . A processing device according to  claim 4 , wherein an instruction set for the first ALU is different from the instruction set of the second ALU. 
     
     
         6 . A processing array according to  claim 3 , wherein the at least one coarse grained logic element includes a coarse grained logic element that comprises an ALU in one direction and an ALU in a direction reverse of the one direction. 
     
     
         7 . A data processing device comprising:
 a multidimensional array of coarse grained logic elements communicating with one another and/or other elements via busses and/or communication lines, wherein:
 at least a first one of said coarse grained logic elements is operated at a first clock rate; 
 at least one of:
 at least one other of said coarse grained logic elements that communicates with said first coarse grained logic element is operated at a second clock rate; and 
 busses and/or communication lines that connect said first coarse grained logic element to other coarse grained logic elements are operated at the second clock rate; 
 
 said first clock rate is higher than said second clock rate; 
 said first coarse grained logic element has data storage means adapted for storage of operands and/or intermediate results; 
 a valid bit is provided for each entry in the storage means, the valid bits being used for controlling data-flow processing by the array. 
   
     
     
         8 . A data processing device comprising:
 a multidimensional array of coarse grained logic elements communicating with one another and/or other elements, at least one of said coarse grained logic elements having data storage means that includes internal registers, each of at least a plurality of the internal registers separately assigned a valid bit indicating whether or not valid data is present in the respective register.   
     
     
         9 . A data processing device comprising:
 a runtime-reconfigurable multidimensional array of coarse grained logic elements communicating with one another and/or other elements, at least one of said coarse grained logic elements having data storage means that includes internal registers, each of at least a plurality of the internal registers separately assigned a valid bit indicating whether or not valid data is present in the respective register.