Method and apparatus for fabricating semiconductor chips using varying areas of precision

Abstract

A system that fabricates a semiconductor chip. The system places patterns for components which require fine line-widths within a high resolution region of a reticle, wherein the high resolution region provides sharp focus for a given wavelength of light used by the lithography system. At the same time, the system places patterns for components which do not require fine line-widths outside of the high-resolution region of the reticle, thereby utilizing the region outside of the high-resolution region of the reticle instead of avoiding the region. Note that the coarseness for components placed outside of the high resolution region of the reticle is increased to compensate for the loss of optical focus outside of the high resolution region.

1 . An apparatus that fabricates a semiconductor chip, comprising:
 a placing mechanism, which is configured to:
 place patterns for components which require fine line-widths within a high-resolution region of a reticle, wherein the high-resolution region provides sharp focus for a given wavelength of light used by the lithography system, wherein a region outside of the high-resolution region provides a lower resolution of optical focus, and wherein the region outside of the high-resolution region surrounds a periphery of the high-resolution region; 
 place patterns for components which do not require fine line-widths within the region outside of the high-resolution region of the reticle; 
 wherein the coarseness for components placed outside of the high-resolution region of the reticle is increased to compensate for the loss of optical focus outside of the high-resolution region. 
   
   
   
       2 . The apparatus of  claim 1 , wherein when placing the patterns for components that require fine line-widths within the high-resolution region of the reticle, the placing mechanism is configured to place patterns for dense, finely-patterned memory structures within the high-resolution region of the reticle. 
   
   
       3 . The apparatus of  claim 1 , wherein when placing the patterns for components which do not require fine line-widths, the placing mechanism is configured to place patterns for coarse wires and coarse transistors outside of the high-resolution region of the reticle. 
   
   
       4 . The apparatus of  claim 1 , wherein when placing the patterns for components which do not require fine line-widths, the placing mechanism is configured to place patterns for capacitively, inductively, or optically coupled terminals outside of the high-resolution region of the reticle. 
   
   
       5 . The apparatus of  claim 1 , wherein the coarseness of patterns placed outside of the high-resolution region of the reticle increases by gradual changes in the minimum dimensions of transistors and wires as the patterns are placed further from the high-resolution region of the reticle. 
   
   
       6 . The apparatus of  claim 1 , wherein the coarseness of patterns placed outside of the high-resolution region of the reticle increases by large focus-steps at the boundary between the high-resolution region of the reticle and the region outside of the high-resolution region of the reticle. 
   
   
       7 . The apparatus of  claim 1 , further comprising:
 multiple large reticles, which have a dense core within a high-resolution region, and which have coarse wires outside of the high-resolution region; and   an imaging mechanism, which is configured to image the large reticles across a wafer by stepping the reticles so that the coarse wires overlap and intersect, thereby obviating the need to use separate lithographic masks for the dense cores and for the coarse wires between the dense cores to create a wafer-scale integration chip.   
   
   
       8 . A semiconductor chip, comprising:
 the semiconductor chip;   wherein the semiconductor chip includes components with fine line-widths located within a high-resolution region for a reticle that is used to manufacture the chip, wherein the high-resolution region provides sharp focus for a given wavelength of light used by the lithography system, wherein a region outside of the high-resolution region provides a lower resolution of optical focus, and wherein the region outside of the high-resolution region surrounds a periphery of the high-resolution region;   wherein the semiconductor chip includes components with coarse line-widths outside of the high-resolution region; and   wherein the coarseness for components located outside of the high-resolution region is increased to compensate for the loss of optical focus outside of the high-resolution region.   
   
   
       9 . The semiconductor chip of  claim 8 , wherein dense, finely-patterned memory structures and other components that use fine line-widths are located within the high-resolution region. 
   
   
       10 . The semiconductor chip of  claim 8 , wherein coarse wires, coarse transistors, and other components that do not require fine line-widths are located outside of the high-resolution region. 
   
   
       11 . The semiconductor chip of  claim 8 , wherein capacitively, inductively, or optically coupled terminals which do not require fine line-widths are located outside of the high-resolution region. 
   
   
       12 . The semiconductor chip of  claim 8 , wherein the coarseness of components located outside of the high-resolution region increases by gradual changes in the minimum dimensions of transistors and wires as the components are located further from the high-resolution region. 
   
   
       13 . The semiconductor chip of  claim 8 , wherein the coarseness of components located outside of the high-resolution region increases by large focus-steps at the boundary between the high-resolution region and the region outside of the high-resolution region. 
   
   
       14 . The semiconductor chip of  claim 8 , further comprising a plurality of dense cores, each located within a high-resolution region;
 wherein each dense core has coarse wires outside of the high-resolution regions; and   wherein a given dense core is coupled to another dense core by overlapping and intersecting the corresponding coarse wires of the dense cores, thereby obviating the need to use separate lithographic masks for the dense cores and for the coarse wires between the dense cores to create a wafer-scale integration chip.