US2010251079A1PendingUtilityA1
Method and device for information block coding and synchronization detecting
Est. expiryMay 26, 2027(~0.9 yrs left)· nominal 20-yr term from priority
H03M 13/6522H03M 13/333H04L 7/041H03M 13/05H03M 13/33H04L 1/0057
39
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
A method and a device for information block coding and synchronization detecting are provided. Information block coding and synchronization detecting are preformed according to a synchronization character sequence satisfying certain conditions. Thus, the probability of incorrect synchronization is effectively reduced without increasing the complexity. Optimal synchronization character sequences in different lengths are provided to further reduce the probability of incorrect synchronization.
Claims
exact text as granted — not AI-modified1 . A method for information block coding, comprising:
obtaining M continuous check information blocks through forward error correction (FEC) coding; adding a synchronization character to each of the M continuous check information blocks according to a synchronization character sequence {Tj}, wherein the synchronization character serves as a synchronization header, wherein the synchronization character added to a jth check information block Pj is Tj, and the synchronization character sequence {Tj} satisfies the following conditions:
∑
i
=
1
M
-
1
Diff
(
T
i
,
T
i
+
1
)
>
1
,
and
∑
i
=
1
M
-
2
Diff
(
T
i
,
T
i
+
2
)
>
0
,
wherein
Diff
(
X
,
Y
)
=
{
0
,
when
X
=
Y
1
,
when
X
≠
Y
,
1
≤
j
≤
M
,
and M is an integer greater than 3.
2 . The method according to claim 1 , wherein
M=4; and the synchronization character sequence {Tj} is {A,B,B,A} or {B,A,A,B}, wherein A is different from B.
3 . The method according to claim 1 , wherein
M=5; and the synchronization character sequence {Tj} is one of the following sequences: {A,A,B,A,B}; {A,A,B,B,A}; {A,B,A,A,B}; {A,B,A,B,B}; {A,B,B,A,A}; {A,B,B,A,B}; {A,B,B,B,A}; {B,A,A,A,B}; {B,A,A,B,A}; {B,A,A,B,B}; {B,A,B,A,A}; {B,A,B,B,A}; {B,B,A,A,B}; {B,B,A,B,A}, wherein A is different from B.
4 . The method according to claim 1 , wherein
M=6; and the synchronization character sequence {Tj} is one of the following sequences: {A,A,B,B,A,B}; {A,B,A,A,B,B}; {A,B,A,B,B,A}; {A,B,B,A,B,A}; {B,A,A,B,A,B}; {B,A,B,A,A,B}; {B,A,B,B,A,A}; {B,B,A,A,B,A}, wherein A is different from B.
5 . The method according to claim 1 , wherein
the information block is a check information block of FEC code word in 10 G EPON, and the synchronization character includes “00” or “11”.
6 . The method according to claim 5 , further comprising:
adding a synchronization header to the data information block, wherein the synchronization header includes a bit, and the bit indicates an information type of the data information block; and wherein the obtaining of M continuous check information blocks comprises: performing FEC coding on a predetermined number of data information blocks and the bit in the synchronization header of the data information blocks to generate M check information blocks.
7 . A device for information block coding, comprising:
a sequence storage module, adapted to store a synchronization character sequence {T j }, wherein the {T j } satisfy the following conditions:
∑
i
=
1
M
-
1
Diff
(
T
i
,
T
i
+
1
)
>
1
,
and
∑
i
=
1
M
-
2
Diff
(
T
i
,
T
i
+
2
)
>
0
,
wherein
Diff
(
X
,
Y
)
=
{
0
,
when
X
=
Y
1
,
when
X
≠
Y
,
1
≤
j
≤
M
,
and M is an integer greater than 3;
an FEC coding module, adapted to generate M continuous check information blocks through FEC coding; and
a first synchronization coding module, adapted to add one synchronization character serving as one synchronization header to each of the M continuous information blocks generated by the FEC coding module according to the synchronization character sequence {T j } stored in the sequence storage module, wherein the synchronization character added to a jth information block P j is T j .
8 . The device according to claim 7 , wherein
M=4; and the synchronization character sequence {T j } is {A,B,B,A} or {B,A,A,B}, wherein A is different from B.
9 . The device according to claim 7 , wherein
M=5; and the synchronization character sequence {Tj} is one of the following sequences: {A,A,B,A,B}; {A,A,B,B,A}; {A,B,A,A,B}; {A,B,A,B,B}; {A,B,B,A,A}; {A,B,B,A,B}; {A,B,B,B,A}; {B,A,A,A,B}; {B,A,A,B,A}; {B,A,A,B,B}; {B,A,B,A,A}; {B,A,B,B,A}; {B,B,A,A,B}; {B,B,A,B,A}, wherein A is different from B.
10 . The device according to claim 7 , wherein, wherein
M=6; and the synchronization character sequence {Tj} is one of the following sequences: {A,A,B,B,A,B}; {A,B,A,A,B,B}; {A,B,A,B,B,A}; {A,B,B,A,B,A}; {B,A,A,B,A,B}; {B,A,B,A,A,B}; {B,A,B,B,A,A}; {B,B,A,A,B,A}, wherein A is different from B.
11 . The device according to claim 7 , wherein the device is a device for coding check information blocks of FEC code words in the 10 G EPON, and the information block is a check information block of FEC code word in 10 G EPON, and the synchronization character includes “00” or “11”.
12 . The device according to claim 11 , further comprising:
a second synchronization coding module, adapted to add a synchronization header to each data information block, wherein the synchronization header contains a bit for indicating a type of the corresponding data information block; an FEC coding module, adapted to perform FEC coding on a predetermined number of data information blocks output by the second synchronization coding module and the bit in the synchronization header of the data information blocks to generate M check information blocks, and output the check information blocks to the first synchronization coding module.Cited by (0)
No later patents cite this yet.
References (0)
No backward citations on record.