US2010251196A1PendingUtilityA1

Method and System for Designing a Structural Level Description of an Electronic Circuit

Assignee: LOGICCON DESIGN AUTOMATION LTDPriority: Sep 2, 2004Filed: Jun 15, 2010Published: Sep 30, 2010
Est. expirySep 2, 2024(expired)· nominal 20-yr term from priority
Inventors:Michael Stern
G06F 30/30
41
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A method and system for designing a structural level description of an electronic circuit with functional behavior described by a plurality of rules, the circuit being specified by data path and control path elements wherein at least one control path element is provided in a form of unresolved variable. The design comprises extracting a plurality of unresolved variables among the control path elements and automated processing of data path and control path elements for accomplishing a state machine formulation, wherein the states of the state machine include states representing at least combinations of unresolved variables and corresponding transitions satisfying said plurality of rules and predefined design criteria.

Claims

exact text as granted — not AI-modified
1 . A method of designing a structural level description of an electronic circuit, the method comprising:
 (a) obtaining data path and control path elements specifying the electronic circuit, wherein at least one control path element is provided in a form of unresolved variable;   (b) obtaining a plurality of rules describing, at least, a functional behavior of the electronic circuit;   (c) extracting a plurality of unresolved variables among the control path elements;   (d) automated processing data path and control path elements for accomplishing a state machine formulation, wherein the states of the state machine include states representing at least combinations of unresolved variables and corresponding transitions satisfying said plurality of rules and predefined design criteria.   
   
   
       2 . The method of  claim 1  wherein the automated processing facilitates correctness-preserving educing of the structural level design. 
   
   
       3 . The method of  claim 1  wherein the predefined design criteria comprise: (a) criterion of logic contradiction; (b) criterion of data integrity; (c) criterion of design flow enabling. 
   
   
       4 . The method of  claim 1  wherein the predefined design criteria comprise constrains introduced for a special purpose. 
   
   
       5 . The method of  claim 4  wherein the special purpose is reduction of power consuming of the electronic circuit. 
   
   
       6 . The method of  claim 1  wherein the structural level description comprises register transfer level description. 
   
   
       7 . The method of  claim 1  wherein the structural description comprises statements in at least one of the languages selected from a group comprising Verilog, VHDL, SystemVerilog and SystemC description. 
   
   
       8 . The method of  claim 1  wherein said plurality of unresolved variables includes all unresolved variables comprised among the control path elements. 
   
   
       9 . The method of  claim 1  wherein the states of the state machine include states representing combinations of resolved and unresolved variables. 
   
   
       10 . A method of designing a structural level description of an electronic circuit, the method comprising:
 (a) obtaining data path and control path elements specifying the electronic circuit, wherein at least one control path element is provided in a form of unresolved variable;   (b) obtaining plurality of rules;   (c) extracting a plurality of unresolved variables among the control path elements;   (d) automated processing of data path and control path elements for obtaining values of unresolved variables satisfying said plurality of rules and predefined design criteria.   
   
   
       11 . The method of  claim 10  wherein the predefined design criteria comprise: (a) criterion of logic contradiction; (b) criterion of data integrity; (c) criterion of design flow enabling. 
   
   
       12 . The method of  claim 10  wherein the predefined design criteria comprise constrains introduced for a special purpose. 
   
   
       13 . The method of  claim 12  wherein the special purpose is reduction of power consuming of the electronic circuit. 
   
   
       14 . The method of  claim 10  wherein the structural level description comprises register transfer level description. 
   
   
       15 . The method of  claim 10  wherein the states of the state machine include states representing combinations of resolved and unresolved variables. 
   
   
       16 . A system for designing a structural level description of an electronic circuit with functional behavior described by a plurality of rules, the circuit being specified by data path and control path elements wherein at least one control path element is provided in a form of unresolved variable; the system comprising a processor for automated processing of data path and control path elements for accomplishing a state machine formulation, wherein the states of the state machine include states representing at least combinations of unresolved variables and corresponding transitions satisfying said plurality of rules and predefined design criteria. 
   
   
       17 . The system of  claim 16  wherein said plurality of unresolved variables includes all unresolved variables comprised among the control path elements. 
   
   
       18 . The system of  claim 16  wherein the states of the state machine include states representing combinations of resolved and unresolved variables. 
   
   
       19 . A computer program comprising computer program code means for performing all the steps of  claim 1  when said program is run on a computer. 
   
   
       20 . A computer program as claimed in  claim 19  embodied on a computer readable medium.

Join the waitlist — get patent alerts

Track US2010251196A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.