Resiliently Retaining State Information Of A Many-Core Processor

Abstract

In one embodiment, the present invention includes a method for performing dynamic testing of a many-core processor including a plurality of cores, manipulating data obtained from the dynamic testing into profile information of the many-core processor, and storing the profile information in a non-volatile memory. The non-volatile memory may be within the many-core processor, in some embodiments. Other embodiments are described and claimed.

1 . A method comprising:
 performing dynamic testing of a many-core processor including a plurality of cores;   manipulating data obtained from the dynamic testing into profile information regarding the many-core processor; and   storing the profile information in a non-volatile memory.   
     
     
         2 . The method of  claim 1 , further comprising partitioning the plurality of cores into a plurality of performance bins based on the dynamic testing, and storing bin information regarding the partitioning in the non-volatile memory. 
     
     
         3 . The method of  claim 1 , wherein the profile information comprises static information regarding operational parameters of each of the plurality of cores. 
     
     
         4 . The method of  claim 3 , further comprising reconfiguring the many-core processor based on updated profile information obtained after a change to at least one of the operational parameters of at least one core. 
     
     
         5 . The method of  claim 4 , wherein reconfiguring the many-core processor comprises reconfiguring an interconnect fabric coupling the plurality of cores based on the updated profile information. 
     
     
         6 . The method of  claim 1 , further comprising:
 accessing the non-volatile memory to obtain the profile information upon initialization of the many-core processor; and   configuring the many-core processor using the profile information.   
     
     
         7 . The method of  claim 1 , further comprising storing resilient state information regarding the many-core processor in the non-volatile memory, the resilient state information including performance bin information for each of the plurality of cores, task allocation information regarding one or more cores allocated to a task, and configuration information regarding an interconnect fabric that couples the plurality of cores. 
     
     
         8 . The method of  claim 1 , further comprising storing the profile information in the non-volatile memory, wherein the non-volatile memory is located on a die of the many-core processor. 
     
     
         9 . An article comprising a machine-readable storage medium including instructions that if executed by a machine enable the machine to perform a method comprising:
 accessing a non-volatile memory to obtain profile information of a many-core processor;   enabling a plurality of cores of the many-core processor based on the profile information; and   configuring an interconnection fabric of the many-core processor based on the profile information to couple the enabled plurality of cores.   
     
     
         10 . The article of  claim 9 , wherein the method further comprises self-testing the many-core processor to determine functional correctness of the enabled plurality of cores. 
     
     
         11 . The article of  claim 10 , wherein the method further comprises:
 disabling one of the enabled plurality of cores after the self-testing and enabling another of the plurality of cores; and   updating the profile information in the non-volatile memory based on the disabling and the enabling.   
     
     
         12 . The article of  claim 11 , wherein the method further comprises reconfiguring the interconnection fabric based on the disabling and enabling and updating the profile information in the non-volatile memory based on the reconfigured interconnection fabric. 
     
     
         13 . A system comprising:
 a many-core processor including a plurality of cores and a non-volatile memory to store resilient state information regarding the plurality of cores, wherein the many-core processor is to access the resilient state information to configure one or more of the plurality of cores for operation; and   a dynamic random access memory (DRAM) coupled to the many-core processor.   
     
     
         14 . The system of  claim 13 , wherein the many-core processor is to perform dynamic self-testing and to update the resilient state information based on the dynamic self-testing. 
     
     
         15 . The system of  claim 14 , wherein the system is to reconfigure the many-core processor based on the updated resilient state information. 
     
     
         16 . The system of  claim 13 , wherein the resilient state information comprises performance bin information for each of the plurality of cores, task allocation information regarding one or more cores allocated to a task, and configuration information regarding an interconnect fabric that couples the plurality of cores. 
     
     
         17 . The system of  claim 13 , wherein the DRAM and the many-core processor are located on a single die, the DRAM comprising a shared memory for the plurality of cores.