Reduced-step cmos processes for low cost radio frequency identification devices

Abstract

Reduced-step CMOS processes for low-cost integrated circuits (ICs) and, more particularly, low-cost radio frequency identification (RFID) devices are disclosed. The CMOS processes disclosed provide sufficient device performance and reliability while reducing the number and complexity of required process steps, thereby reducing the cost for manufacturing ICs. By recognizing the particular needs for low-cost integrated circuits such as RFID devices (for example, reduced needs for performance, power and longevity) and by identifying a reduced set of CMOS process steps, an advantageous solution is achieved for producing low-cost integrated circuits and low-cost RFID devices.

1 . A low-cost CMOS integrated circuit, comprising:
 first-type MOS transistors formed within a second-type semiconductor substrate without utilizing a lightly doped drain (LDD) process;   second-type MOS transistors formed in first-type well regions within the substrate without utilizing a LDD process; and   interconnect circuitry comprising non-silicide and non-salicide polysilicon layers and two or fewer metal interconnect layers.   
     
     
         2 . The low-cost CMOS integrated circuit of  claim 1 , wherein the first-type is N-type, the second-type is P-type, the first-type MOS transistors are NMOS transistors, and the second-type MOS transistors are PMOS transistors. 
     
     
         3 . The low-cost CMOS integrated circuit of  claim 2 , wherein the NMOS transistors have controlled threshold voltages and the PMOS transistors have varied threshold voltages. 
     
     
         4 . The low-cost CMOS integrated circuit of  claim 1 , wherein the first-type is P-type, the second-type is N-type, the first-type MOS transistors are PMOS transistors, and the second-type MOS transistors are NMOS transistors. 
     
     
         5 . The low-cost CMOS integrated circuit of  claim 4 , wherein the NMOS transistors have controlled threshold voltages and the PMOS transistors have varied threshold voltages. 
     
     
         6 . The low-cost CMOS integrated circuit of  claim 1 , wherein the integrated circuit has a minimum device geometry of 1.0 microns or less. 
     
     
         7 . The low-cost CMOS integrated circuit of  claim 1 , wherein the integrated circuit has a minimum device geometry of 0.5 microns or less. 
     
     
         8 . The low-cost CMOS integrated circuit of  claim 1 , wherein the integrated circuit comprises an integrated radio frequency identification (RFID) device. 
     
     
         9 . The low-cost CMOS integrated circuit of  claim 8 , wherein the interconnect circuitry for the integrated circuit was formed without utilizing metal plugs to fill contact holes. 
     
     
         10 . The low-cost CMOS integrated circuit of  claim 8 , wherein the interconnect circuitry for the integrated circuit was formed without utilizing a Chemical Mechanical Polishing (CMP) process step. 
     
     
         11 . The low-cost CMOS integrated circuit of  claim 8 , wherein the first-type MOS and the second-type MOS transistors are not separated by a field implant. 
     
     
         12 . The low-cost CMOS integrated circuit of  claim 8 , further comprising embedded memory within the RFID device. 
     
     
         13 . The low-cost CMOS integrated circuit of  claim 12 , wherein the embedded memory comprises non-volatile memory. 
     
     
         14 . The low-cost CMOS integrated circuit of  claim 8 , further comprising an antenna integrated with the RFID device. 
     
     
         15 . The low-cost CMOS integrated circuit of  claim 8 , wherein the RFID device does not include electrostatic discharge (ESD) protection circuitry. 
     
     
         16 . The low-cost CMOS integrated circuit of  claim 1 , wherein the substrate does not include a lightly doped epitaxial (EPI) layer. 
     
     
         17 . The low-cost CMOS integrated circuit of  claim 8 , wherein the RFID device further comprises power circuitry, receive path circuitry, transmit path circuitry and logic circuitry. 
     
     
         18 . The low-cost CMOS integrated circuit of  claim 17 , wherein the RFID device costs five cents or fewer to fabricate. 
     
     
         19 . The low-cost CMOS integrated circuit of  claim 17 , wherein the circuitry is configured at least in part to account for the varied threshold voltages for the second-type MOS transistors. 
     
     
         20 . The low-cost CMOS integrated circuit of  claim 8 , wherein the first-type MOS and the second-type MOS transistors are not separated by a field implant, wherein the interconnect circuitry for the integrated circuit was formed without utilizing a Chemical Mechanical Polishing (CMP) process step, wherein the RFID device does not include electrostatic discharge (ESD) protection circuitry, and wherein the substrate does not include a lightly doped epitaxial (EPI) layer.