Receiver for wireless communication system

Abstract

One exemplary receiver for a wireless communication system includes a plurality of signal processing components arranged to generate a receiver output according to a radio frequency (RF) signal. The signal processing components include amplifiers having a class-AB biased amplifier included therein. The signal processing components are disposed in a chip, and the class-AB biased amplifier is an amplifier which processes a signal corresponding to the RF signal before any other amplifier included in the chip. Another exemplary receiver for a wireless communication system includes an RF signal processor and a frequency conversion interface. The RF signal processor is to generate an RF signal, and has a class-AB biased amplifier arranged to apply amplification upon the RF signal. The frequency conversion interface is coupled to the RF signal processor, and used for receiving the RF signal generated from the RF signal processor and generating a down-converted result of the RF signal.

1 . A receiver for a wireless communication system, comprising:
 a plurality of signal processing components, arranged to generate a receiver output according to a radio frequency (RF) signal, the signal processing components comprising amplifiers having a class-AB biased amplifier included therein;   wherein the signal processing components are disposed in a chip, and the class-AB biased amplifier is an amplifier which processes a signal corresponding to the RF signal before any other amplifier included in the chip.   
     
     
         2 . The receiver of  claim 1 , wherein the class-AB biased amplifier has an input port and an output port, and comprises:
 a first amplifier block, coupled to the input port, for receiving an input at the input port;   a bias circuit, coupled to the first amplifier block and arranged to bias the first amplifier block for a class-AB operation; and   a second amplifier block, coupled to the first amplifier block and the output port, for generating an output at the output port;   wherein the first amplifier block comprises at least a transistor having a control terminal coupled to the bias circuit and thus biased by the bias circuit; and the transistor has an exponential current versus voltage characteristic.   
     
     
         3 . The receiver of  claim 2 , wherein the transistor is a metal-oxide-semiconductor (MOS) transistor biased by the bias circuit to operate in a weak inversion region. 
     
     
         4 . The receiver of  claim 2 , wherein the transistor is a bipolar junction transistor (BJT). 
     
     
         5 . The receiver of  claim 1 , wherein the class-AB biased amplifier has an input port and an output port, and comprises:
 a first amplifier block, coupled to the input port, for receiving an input at the input port;   a bias circuit, coupled to the first amplifier block and arranged to bias the first amplifier block for a class-AB operation; and   a second amplifier block, coupled to the first amplifier block and the output port, for generating an output at the output port;   wherein the first amplifier block comprises at least a transistor having a control terminal coupled to the bias circuit and thus biased by the bias circuit;   and a bias current passing through the transistor changes automatically in response to an input power level change, without any detection and feedback circuitry applied thereto.   
     
     
         6 . The receiver of  claim 5 , wherein the transistor is a metal-oxide-semiconductor (MOS) transistor biased by the bias circuit to operate in a weak inversion region. 
     
     
         7 . The receiver of  claim 5 , wherein the transistor is a bipolar junction transistor (BJT). 
     
     
         8 . The receiver of  claim 1 , wherein the signal processing components belong to an RF signal processor and a frequency conversion interface, the RF signal processor is configured to generate the RF signal and includes the class-AB biased amplifier arranged to apply amplification upon the RF signal, and the frequency conversion interface is coupled to the RF signal processor and arranged to receive the RF signal generated from the RF signal processor and generate a down-converted result of the RF signal. 
     
     
         9 . The receiver of  claim 8 , wherein the class-AB biased amplifier is a transconductance amplifier, and the frequency conversion interface is operated as a current driven interface to the RF signal processor for an output-of-band part of the RF signal. 
     
     
         10 . The receiver of  claim 9 , wherein the frequency conversion interface is further arranged to reduce a voltage swing of the output-of-band part in the RF signal so as to prevent the RF signal processor from being saturated by the out-of-band part of the RF signal. 
     
     
         11 . The receiver of  claim 8 , further comprising:
 a blocking circuit, coupled between the RF signal processor and the frequency conversion interface, for direct current (DC) blocking of the RF signal.   
     
     
         12 . A receiver for a wireless communication system, comprising:
 a radio frequency (RF) signal processor, configured to provide an RF signal, comprising:
 a class-AB biased amplifier, arranged to apply amplification upon the RF signal; and 
   a frequency conversion interface, coupled to the RF signal processor, for receiving the RF signal generated from the RF signal processor and generating a down-converted result of the RF signal.   
     
     
         13 . The receiver of  claim 12 , wherein the class-AB biased amplifier has an input port and an output port, and comprises:
 a first amplifier block, coupled to the input port, for receiving an input at the input port;   a bias circuit, coupled to the first amplifier block and arranged to bias the first amplifier block for a class-AB operation; and   a second amplifier block, coupled to the first amplifier block and the output port, for generating an output at the output port;   wherein the first amplifier block comprises at least a transistor having a control terminal coupled to the bias circuit and thus biased by the bias circuit;   and the transistor has an exponential current versus voltage characteristic.   
     
     
         14 . The receiver of  claim 13 , wherein the transistor is a metal-oxide-semiconductor (MOS) transistor biased by the bias circuit to operate in a weak inversion region. 
     
     
         15 . The receiver of  claim 13 , wherein the transistor is a bipolar junction transistor (BJT). 
     
     
         16 . The receiver of  claim 12 , wherein the class-AB biased amplifier has an input port and an output port, and comprises:
 a first amplifier block, coupled to the input port, for receiving an input at the input port;   a bias circuit, coupled to the first amplifier block and arranged to bias the first amplifier block for a class-AB operation; and   a second amplifier block, coupled to the first amplifier block and the output port, for generating an output at the output port;   wherein the first amplifier block comprises at least a transistor having a control terminal coupled to the bias circuit and thus biased by the bias circuit;   and a bias current passing through the transistor changes automatically in response to an input power level change, without any detection and feedback circuitry applied thereto.   
     
     
         17 . The receiver of  claim 16 , wherein the transistor is a metal-oxide-semiconductor (MOS) transistor biased by the bias circuit to operate in a weak inversion region. 
     
     
         18 . The receiver of  claim 16 , wherein the transistor is a bipolar junction transistor (BJT). 
     
     
         19 . The receiver of  claim 12 , wherein the class-AB biased amplifier is a transconductance amplifier, and the frequency conversion interface is operated as a current driven interface to the RF signal processor for an output-of-band part of the RF signal. 
     
     
         20 . The receiver of  claim 19 , wherein the frequency conversion interface is further arranged to reduce a voltage swing of the output-of-band part in the RF signal so as to prevent the RF processor from being saturated by the out-of-band part of the RF signal. 
     
     
         21 . The receiver of  claim 12 , further comprising:
 a blocking circuit, coupled between the RF signal processor and the frequency conversion interface, for direct current (DC) blocking of the RF signal.   
     
     
         22 . An amplifier, comprising:
 a first amplifier block, coupled to an input port and an output port of the amplifier and arranged to amplify an input, the first amplifier block having an input stage arranged to receive the input at the input port of the amplifier;   a second amplifier block, coupled to the input port and the output port of the amplifier and arranged to amplify the input, the second amplifier block comprising:
 a first input stage, arranged to receive the input at the input port of the amplifier; and 
 a first switch unit, coupled to the first input stage, wherein the first switch unit selectively couples an output node of the first input stage to the output port of the amplifier or a reference voltage; 
   a bias circuit, coupled to the first amplifier block and the second amplifier block, for biasing the first amplifier block and the second amplifier block; and   a switch controller, arranged to control operation of at least the first switch unit;   wherein when the amplifier enters a first gain mode, the bias circuit applies a class-A bias to each of the input stage in the first amplifier block and the first input stage in the second amplifier block, and the switch controller controls the first switch unit to couple the output node of the first input stage to the reference voltage.   
     
     
         23 . The amplifier of  claim 22 , wherein the second amplifier block further comprises:
 a second input stage, arranged to receive the input at the input port of the amplifier; and   a second switch unit, coupled to the second input stage, for selectively coupling an output node of the second input stage to the output port of the amplifier or the reference voltage;   wherein when the amplifier enters the first gain mode, the bias circuit further applies the class-A bias to the second input stage, and the switch controller further controls the second switch unit to couple the output node of the second input stage to the reference voltage; and when the amplifier enters a second gain mode, the bias circuit applies a class-AB bias to each of the input stage in the first amplifier block and the first input stage and the second input stage in the second amplifier block, and the switch controller controls the first switch unit to couple the output node of the first input stage to the reference voltage and controls the second switch unit to couple the output node of the second input stage to the output port of the amplifier.   
     
     
         24 . The amplifier of  claim 23 , wherein the second amplifier block further comprises:
 a third input stage, arranged to receive the input at the input port of the amplifier; and   a third switch unit, coupled to the third input stage, for coupling an output node of the third input stage to the output port of the amplifier or the reference voltage;   wherein when the amplifier enters the first gain mode, the switch controller further controls the third switch unit to disconnect the output node of the third input stage from both of the reference voltage and the output port of the amplifier; and when the amplifier enters the second gain mode, the bias circuit further applies the class-AB bias to the third input stage, and the switch controller further controls the third switch unit to couple the output node of the third input stage to the reference voltage.   
     
     
         25 . The amplifier of  claim 24 , wherein when the amplifier enters a third gain mode, the bias circuit applies a class-AB bias to each of the input stage in the first amplifier block and the first input stage, the second input stage and the third input stage in the second amplifier block, and the switch controller controls the first switch unit to couple the output node of the first input stage to the output port of the amplifier, controls the second switch unit to couple the output node of the second input stage to the output port of the amplifier, and controls the third switch unit to couple the output node of the third input stage to the output port of the amplifier. 
     
     
         26 . The amplifier of  claim 23 , wherein when the amplifier enters a third gain mode, the bias circuit applies a class-AB bias to each of the input stage in the first amplifier block and the first input stage and the second input stage in the second amplifier block, and the switch controller controls the first switch unit to couple the output node of the first input stage to the output port of the amplifier and controls the second switch unit to couple the output node of the second input stage to the output port of the amplifier. 
     
     
         27 . The amplifier of  claim 22 , wherein when the amplifier enters a second gain mode, the bias circuit applies a class-AB bias to each of the input stage in the first amplifier block and the first input stage in the second amplifier block, and the switch controller controls the first switch unit to couple the output node of the first input stage to the output port of the amplifier. 
     
     
         28 . The amplifier of  claim 27 , wherein the second amplifier block further comprises:
 a second input stage, arranged to receive the input at the input port of the amplifier; and   a second switch unit, coupled to the second input stage, for coupling an output node of the second input stage to the output port of the amplifier or the reference voltage;   wherein when the amplifier enters the first gain mode, the switch controller further controls the second switch unit to disconnect the output node of the second input stage from both of the reference voltage and the output port of the amplifier; and when the amplifier enters the second gain mode, the bias circuit further applies the class-AB bias to the second input stage, and the switch controller further controls the second switch unit to couple the output node of the second input stage to the output port of the amplifier.   
     
     
         29 . An amplifier, comprising:
 a first amplifier block, coupled to an input port and an output port of the amplifier and arranged to amplify an input, the first amplifier block having an input stage arranged to receive the input at the input port of the amplifier;   a second amplifier block, coupled to the input port and the output port of the amplifier and arranged to amplify the input, the second amplifier block comprising:
 a plurality of input stages, each arranged to receive the input at the input port of the amplifier; and 
 a plurality of switch units, respectively coupled to the input stages, wherein each of the switch unit controls a connection of an output node of a corresponding input stage; 
   a bias circuit, coupled to the first amplifier block and the second amplifier block, for biasing the first amplifier block and the second amplifier block; and   a switch controller, arranged to control operation of the switch units;   wherein when an input power of the input exceeds a predetermined level, the bias circuit applies a class-A bias to each of the input stage in the first amplifier block and the input stages in the second amplifier block, the switch controller controls the switch units to disconnect output nodes of the input stages in the second amplifier block from the output port of the amplifier, and at least one input stage in the second amplifier block is disabled by at least one switch unit controlled by the switch controller.   
     
     
         30 . An amplifier, comprising:
 a first amplifier block, coupled to an input port and an output port of the amplifier and arranged to amplify an input, the first amplifier block having a first input stage arranged to receive the input at the input port of the amplifier;   a second amplifier block, coupled to the input port and the output port of the amplifier, the second amplifier block comprising:
 a second input stage, arranged to receive the input at the input port of the amplifier; and 
 a switch unit, coupled to the second input stage and arranged to control a connection of an output node of the second input stage; 
   a bias circuit, coupled to the first amplifier block and the second amplifier block, for biasing the first amplifier block and the second amplifier block; and   a switch controller, arranged to control operation of the switch unit;   wherein when an input power of the input exceeds a predetermined level, the bias circuit applies a class-AB bias to each of the first input stage and the second input stage, and the second input stage is disabled by the switch unit controlled by the switch controller.