risc processor device and its instruction address conversion looking-up method

Abstract

An RISC processor and a method for converting and looking-up instruction address in the RISC processor. The device comprises a decoder, which includes a look-up table module for realizing the conversion from an X86 source instruction address to an MIPS target instruction address by using a look-up table. The look-up table module includes: a looking-up sub-module for indexing the look-up table based on content, wherein if looking-up is hit, the corresponding content will be stored in a target register, and if not, an entry address of the not-hit service program will be stored in the target register; and an indexing sub-module for indexing the look-up table based on content and getting an index of the table entry in which the content resides.

1 . An RISC processor device comprising a decoder, characterized in that the decoder includes a look-up table module for realizing the conversion from an X86 source instruction address to an MIPS target instruction address by using a look-up table. 
     
     
         2 . The RISC processor device according to  claim 1 , characterized in that the look-up table module includes a looking-up sub-module and an indexing sub-module, wherein
 the looking-up sub-module is adapted for indexing the look-up table based on content, wherein if a table entry is hit, the corresponding content will be stored in a target register, and if not, an entry address of the not-hit service program will be stored in the target register, and   the indexing sub-module is adapted for indexing the look-up table based on content and getting an index of the table item in which the content resides.   
     
     
         3 . The RISC processor device according to  claim 2 , characterized in that the look-up table module further includes a filling-in sub-module adapted for filling in the look-up table based on an index of a table entry of the look-up table. 
     
     
         4 . The RISC processor device according to  claim 3 , characterized in that the look-up table module further includes a reading sub-module adapted for reading the content of the look-up table based on an index of a table entry of the look-up table. 
     
     
         5 . The RISC processor device according to  claim 1 , characterized in that the look-up table is a content addressable look-up table and realized by using a content addressable memory or a random access memory. 
     
     
         6 . The RISC processor device according to  claim 5 , characterized in that the look-up table includes 3 domains, namely, Domain ASID, Domain SPC and Domain TPC, wherein
 Domain ASID is adapted for storing the ID numbers for initiating a plurality of processes of an X86 virtual machine on an operating system, Domain SPC is adapted for storing X86 source instruction addresses, and Domain TPC is adapted for storing MIPS target instruction addresses.   
     
     
         7 . The RISC processor device according to  claim 2 , characterized in that the entry address of the not-hit service program is a default value provided by the virtual machine, which value is stored either in CAM.default of a CP0 register or in Item No. 0 of the look-up table. 
     
     
         8 . A method for converting and looking-up instruction address in an RISC processor comprising a decoder which includes a look-up table module for realizing the conversion from an X86 source instruction address to an MIPS target instruction address by using a look-up table,
 characterized in that the method comprises the following steps:   Step A: when an X86 virtual machine of the RISC processor starts up, initializing the look-up table and filling in the look-up table using the content of the obtained instruction address of the X86 virtual machine to the MIPS instruction address; and   Step B: accessing the look-up table to complete the conversion from the X86 source instruction address to the target instruction address while executing a jump instruction in the X86 virtual machine of the RISC processor.   
     
     
         9 . The method according to  claim 8 , characterized in that the Step B includes the following steps:
 Step B1: using a CAMPV instruction for querying a table entry value of the look-up table to search the look-up table according to the source instruction address in the register to thereby obtain the target instruction address;   Step B2: if the looking-up is hit, storing the value of the directly obtained target instruction address in a target register and jumping by using the jump instruction to the code segment pointed by the target address to continue the execution; and   Step B3: if the looking-up is not hit, storing the obtained address of the not-hit service program, which address is provided by the virtual machine, in the target register and jumping to the not-hit service program to continue the execution.   
     
     
         10 . The method according to  claim 9 , characterized in that the following step is further included after the Step B3:
 Step C: the not-hit service program refilling in the look-up table based on the content of a hash table maintained by the virtual machine.   
     
     
         11 . The method according to  claim 10 , characterized in that the Step C includes the following steps:
 Step C1: using a CAMPI instruction for querying an index of a table entry of the look-up table to obtain an index of the table entry in which a value of the source instruction address resides, and storing the index in the target register; and   Step C2: using a CAMWI instruction for filling in a look-up table based on an index of a table entry of the look-up table to fill in the table with an ASID of a progress, a source instruction address and a corresponding target instruction address based on a value of the index in the target register.   
     
     
         12 . The method according to  claim 11 , characterized in that the following step is further included after the Step C2:
 Step D: invalidating one item of content in the look-up table, or reading the content of the look-up table RAM based on an index of a table entry of the look-up table.   
     
     
         13 . The RISC processor device according to  claim 2 , characterized in that the look-up table is a content addressable look-up table and realized by using a content addressable memory or a random access memory. 
     
     
         14 . The RISC processor device according to  claim 3 , characterized in that the look-up table is a content addressable look-up table and realized by using a content addressable memory or a random access memory. 
     
     
         15 . The RISC processor device according to  claim 4 , characterized in that the look-up table is a content addressable look-up table and realized by using a content addressable memory or a random access memory. 
     
     
         16 . The RISC processor device according to  claim 13 , characterized in that the look-up table includes 3 domains, namely, Domain ASID, Domain SPC and Domain TPC, wherein
 Domain ASID is adapted for storing the ID numbers for initiating a plurality of processes of an X86 virtual machine on an operating system, Domain SPC is adapted for storing X86 source instruction addresses, and Domain TPC is adapted for storing MIPS target instruction addresses.   
     
     
         17 . The RISC processor device according to  claim 14 , characterized in that the look-up table includes 3 domains, namely, Domain ASID, Domain SPC and Domain TPC, wherein
 Domain ASID is adapted for storing the ID numbers for initiating a plurality of processes of an X86 virtual machine on an operating system, Domain SPC is adapted for storing X86 source instruction addresses, and Domain TPC is adapted for storing MIPS target instruction addresses.   
     
     
         18 . The RISC processor device according to  claim 15 , characterized in that the look-up table includes 3 domains, namely, Domain ASID, Domain SPC and Domain TPC, wherein
 Domain ASID is adapted for storing the ID numbers for initiating a plurality of processes of an X86 virtual machine on an operating system, Domain SPC is adapted for storing X86 source instruction addresses, and Domain TPC is adapted for storing MIPS target instruction addresses.