Light emitting diode element and method for fabricating the same

Abstract

The present invention discloses a light emitting diode (LED) element and a method for fabricating the same, which can promote light extraction efficiency of LED, wherein a substrate is etched to obtain basins with inclined natural crystal planes, and an LED epitaxial structure is selectively formed inside the basin. Thereby, an LED element having several inclines is obtained. Via the inclines, the probability of total internal reflection is reduced, and the light extraction efficiency of LED is promoted.

1 . A light emitting diode element comprising:
 a light emitting diode structure with inclines formed via etching a substrate to obtain basins having inclined natural crystal planes and a bottom plane, and epitaxially growing on said bottom plane an n-type III-V group compound layer, an active layer and a p-type III-V group compound layer in sequence, wherein said active layer is interposed between said n-type III-V group compound layer and said p-type III-V group compound layer and functions as a light emitting zone;   a p-type ohmic contact metal layer formed on said p-type III-V group compound layer;   a heat-conduction substrate connected with said p-type ohmic contact metal layer; and   an n-type ohmic contact metal layer formed on said n-type III-V group compound layer.   
     
     
         2 . The light emitting diode element according to  claim 1 , wherein said light emitting diode structure has a shape of a rectangle, circle, triangle, star, or polygon. 
     
     
         3 . The light emitting diode element according to  claim 1 , wherein said light emitting diode structure has a thickness of between 0.5 and 50 microns and has a diameter of between 200 and 2000 microns. 
     
     
         4 . The light emitting diode element according to  claim 1 , wherein said n-type III-V group compound layer has a rugged surface. 
     
     
         5 . The light emitting diode element according to  claim 1 , wherein said active layer is a dual heterogeneous (DH) junction structure, a single quantum well (SQW) structure or a multiple quantum well (MQW) structure.