System and method to reduce noise in a substrate

Abstract

A system for reducing noise in a chip is disclosed and may include a substrate, a first well disposed on top of the substrate, a second well and a third well that are both disposed within the first well, a first transistor disposed in the second well, a positive potential of a voltage source connected to a body of the first transistor, and a second transistor disposed in the third well. The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor. A noisy voltage source may be coupled to a source of the first transistor. A body of the first transistor may be resistively coupled to the second well. The system may include a noisy voltage source, where a body and a source of the second transistor are both coupled to the noisy voltage source.

1 - 15 . (canceled) 
     
     
         16 . A system for reducing noise in a chip, the system comprising:
 a substrate;   a first well disposed on top of said substrate;   a second well and a third well that are both disposed within said first well;   a first transistor disposed in said second well;   a positive potential of a voltage source connected to a body of said first transistor; and   a second transistor disposed in said third well.   
     
     
         17 . The system according to  claim 16 , wherein said first transistor is a PMOS transistor. 
     
     
         18 . The system according to  claim 16 , wherein said second transistor is an NMOS transistor. 
     
     
         19 . The system according to  claim 16 , comprising a noisy voltage source coupled to a source of said first transistor. 
     
     
         20 . The system according to  claim 16 , wherein a body of said first transistor is resistively coupled to said second well. 
     
     
         21 . The system according to  claim 16 , comprising a noisy voltage source, wherein a body and a source of said second transistor are both coupled to said noisy voltage source. 
     
     
         22 . The system according to  claim 16 , wherein a body of said second transistor is capacitively coupled to said substrate. 
     
     
         23 . The system according to  claim 16 , wherein said first well is a deep well. 
     
     
         24 . The system according to  claim 16 , wherein said substrate is doped with a first dopant. 
     
     
         25 . The system according to  claim 16 , wherein said first well is doped with a second dopant. 
     
     
         26 . The system according to  claim 16 , wherein said second well is doped with a second dopant. 
     
     
         27 . The system according to  claim 16 , wherein said third well is doped with a first dopant. 
     
     
         28 . A system for reducing noise in a chip, the system comprising:
 a substrate;   a first well disposed on top of said substrate;   a second well and a third well that are both disposed within said first well;   a first transistor disposed in said second well;   a positive potential of a first voltage source connected to a body of said first transistor;   a second transistor disposed in said third well; and   a negative potential of a second voltage source connected to a body of said second transistor.   
     
     
         29 . The system according to  claim 28 , wherein said negative potential of said second voltage source is connected to a source of said second transistor. 
     
     
         30 . The system according to  claim 29 , wherein said second voltage source comprises a noisy voltage source, wherein said body and said source of said second transistor are both coupled to said noisy voltage source. 
     
     
         31 . The system according to  claim 28 , wherein a positive potential of a third voltage source is connected to a source of said first transistor. 
     
     
         32 . The system according to  claim 31 , wherein said third voltage source comprises a noisy voltage source. 
     
     
         33 . The system according to  claim 28 , wherein said first transistor is a PMOS transistor. 
     
     
         34 . The system according to  claim 28 , wherein said second transistor is an NMOS transistor. 
     
     
         35 . The system according to  claim 28 , wherein a body of said first transistor is resistively coupled to said second well. 
     
     
         36 . The system according to  claim 28 , wherein a body of said second transistor is capacitively coupled to said substrate. 
     
     
         37 . The system according to  claim 28 , wherein said first well is a deep well. 
     
     
         38 . The system according to  claim 28 , wherein said substrate is doped with a first dopant. 
     
     
         39 . The system according to  claim 28 , wherein said first well is doped with a second dopant. 
     
     
         40 . The system according to  claim 28 , wherein said second well is doped with a second dopant. 
     
     
         41 . The system according to  claim 28 , wherein said third well is doped with a first dopant.