Increased grain size in metal wiring structures through flash tube irradiation

Abstract

A method for forming a wiring structure includes forming a metal layer on a substrate, and annealing the metal layer by irradiating the metal layer with light emitted from at least one flash tube, thereby growing crystalline grains of the metal layer.

1 . A wiring structure having a plurality of thin film transistors, comprising:
 an insulating substrate;   a first insulating layer formed on the substrate;   a plurality of scanning lines including gate electrodes formed on the first insulating substrate;   a second insulating layer covering the scanning lines and the first insulating layer;   a plurality of semiconductor layers formed on the second insulating layer;   source and drain electrodes connected with each of the semiconductor layer; and   a plurality of signal lines electrically connected with the drain electrodes, wherein   each of the scanning lines includes a barrier metal layer formed on the first insulating layer, and a metal layer essentially comprising a copper material and disposed on a top surface of the barrier metal layer, of which main crystalline orientation is ( 111 ) face, and   the second insulating layer includes silicon nitride.   
     
     
         2 . The wiring structure according to  claim 1 , wherein the metal layer comprises pure copper. 
     
     
         3 . The wiring structure according to  claim 1 , wherein the metal layer includes at least one selected from magnesium, titanium, molybdenum, tantalum and chromium. 
     
     
         4 . The wiring structure according to  claim 1 , wherein a resistance of the metal layer is in the range of 1.7 to 1.8 μΩcm. 
     
     
         5 . The wiring structure according to  claim 1 , wherein the barrier metal layer and the metal layer are continuously formed in accordance with a sputtering method. 
     
     
         6 . The wiring structure according to  claim 1 , further comprising pixel electrodes electrically connected with the source electrodes respectively. 
     
     
         7 . A wiring structure having a plurality of thin film transistors, comprising:
 an insulating substrate;   a first insulating layer formed on the substrate;   a plurality of scanning lines including gate electrodes formed on the first insulating substrate;   a second insulating layer covering the scanning lines and the first insulating layer;   a plurality of semiconductors layer formed on the second insulating layer;   source and drain electrodes connected with each of the semiconductor layer; and   a plurality of signal lines electrically connected with the drain electrodes, wherein   each of the scanning lines includes a barrier oxide layer and a metal layer essentially comprises copper material disposed on a top surface of the barrier oxide layer, of which main crystalline orientation is (111) face, and   the second insulating layer includes silicon nitride.   
     
     
         8 . The wiring structure according to  claim 7 , wherein the metal layer includes at least one selected from magnesium, titanium, molybdenum, tantalum and chromium. 
     
     
         9 . The wiring structure according to  claim 7 , wherein a resistance of the metal layer is in the range of 1.7 to 1.8 μΩcm. 
     
     
         10 . The wiring structure according to  claim 7 , further comprising pixel electrodes electrically connected with source electrodes respectively.