Method of fabricating solar cell chips

Abstract

A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips.

1 . A method, comprising:
 creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility;   creating a solar cell process route for fabricating solar cells using solar cell wafers in said integrated circuit fabrication facility;   releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of said an integrated circuit fabrication facility; and   processing said solar cell wafers on at least some tools of said integrated circuit fabrication facility used to process said integrated circuit wafers.   
     
     
         2 . The method of  claim 1 , further including:
 when both solar cell wafers and integrated circuit wafers are present in a same tool queue of a particular tool of said integrated circuit fabricating facility, processing said integrated circuit wafers on said particular tool before processing said solar cell wafers on said particular tool.   
     
     
         3 . The method of  claim 1 , further including:
 when both solar cell wafers and integrated circuit wafers are present in a same tool queue of a particular tool of said integrated circuit fabricating facility, processing said integrated circuit wafers on said particular tool before processing said solar cell wafers on said particular tool except if a particular solar cell wafer has been in said particular tool queue for greater than a target time, then processing that particular solar cell wafer before any integrated circuit wafers in said tool queue of said particular tool.   
     
     
         4 . The method of  claim 1 , further including;
 selecting scrap integrated circuit wafers from said integrated circuit fabrication facility; and   recycling said scrap integrated circuit wafers to form said solar cell wafers.   
     
     
         5 . The method of  claim 4 , wherein said recycling includes:
 etching said scrap integrated circuit wafers;   after said etching, grinding said scrap integrated circuit wafers; and   after said grinding, chemical-mechanical-polishing said scrap integrated circuit wafers.   
     
     
         6 . The method of  claim 1 , further including:
 singulating said solar cell wafers into individual solar cell chips.   
     
     
         7 . The method of  claim 6 , wherein said solar cell chips range in surface area from about 25 mm 2  to about 400 mm 2 . 
     
     
         8 . The method of  claim 1 , wherein said solar cell wafers are additionally processed on one or more tools used only for fabricating solar cell chips. 
     
     
         9 . The method of  claim 1 , wherein after processing said solar cell wafers up to a singulating step, said solar cell wafers include solar cell chips having different surface areas. 
     
     
         10 . The method of  claim 1 , further including performing the following process steps on said solar cell wafers:
 forming a P-doped layer and an N-doped layer in a solar cell wafer, said P-doped layer adjacent to a top surface of said solar cell wafer and said N-doped layer adjacent to a bottom surface of said solar cell wafer;   forming a dielectric top passivation layer on said top surface of said solar cell wafer and a dielectric bottom passivation layer on said top surface of said solar cell wafer;   forming an antireflective coating on said top passivation layer;   photolithographically forming a first set of openings through said antireflective coating and through said top passivation layer to said P-doped layer and photolithographically forming a second set of openings through said bottom passivation layer to said N-doped layer;   forming first metal silicide contacts to said P-doped layer and second metal silicide contacts to said N-doped layer in said first and second openings respectively; and   forming metal contact frames on said first metal silicide contacts and metal bus bars on said second metal silicide contacts.   
     
     
         11 . The method of  claim 10 :
 wherein said photolithographically forming said first set of openings includes defining first openings in a first hardmask layer and after forming said first set of opening, removing said hardmask layer; and   wherein said photolithographically forming said second set of openings includes defining second openings in a second hardmask layer and after forming said second set of opening, removing said hardmask layer.   
     
     
         12 . The method of  claim 1 , wherein said bus bar is a plate. 
     
     
         13 . The method of  claim 1 , wherein said bus bar comprises a grid of intersecting orthogonal wires. 
     
     
         14 . The method of  claim 1 , wherein said bus bar comprises a set of parallel wires.