Architecture of Function Blocks and Wirings in a Structured ASIC and Configurable Driver Cell of a Logic Cell Zone

Abstract

An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.

1 . An application-specific integrated semiconductor circuit (ASIC), comprising:
 an array of logic function blocks disposed in a substrate and in a first wiring layer, the first wiring layer at least partially defining a function of the logic function block; and   an array of wiring zones corresponding to the array of logic function blocks, the array of wiring zones serving for routing signals between the array of logic function blocks, the array of wiring zones disposed in at least two wiring layers comprising wiring lines, wherein the wiring lines in the at least two wiring layers are not parallel to one another, wherein the wiring lines in at least one of the two wiring layers comprise line segments that are continuous within a wiring zone of the array of wiring zones, and wherein the line segments are interrupted at wiring zone boundaries.   
     
     
         2 . The ASIC according to  claim 1 , wherein the wiring lines in the other of the at least two wiring layers comprise line segments that are continuous within a wiring zone, and wherein the line segments of the other of the at least two wiring layers are interrupted at wiring zone boundaries. 
     
     
         3 . The ASIC according to  claim 1 , wherein at least two wiring layers of a wiring zone are situated directly above the first wiring layer for a definitive definition of the function of the logic function block. 
     
     
         4 . The ASIC according to  claim 1 , wherein a definitive definition of the function of the logic function block is effected by at least one further wiring layer or a configurable connection in an insulation layer. 
     
     
         5 . The ASIC according to  claim 4 , wherein the further wiring layer is situated directly above the first wiring layer, and wherein the further wiring layer coincides with the bottommost one of the at least two wiring layers of a wiring zone. 
     
     
         6 . The ASIC according to  claim 4 , wherein the configurable connection coincides with the insulation layer between the at least two wiring layers. 
     
     
         7 . The ASIC according to  claim 4 , wherein the configurable connection coincides with the insulation layer directly below a lower wiring layer of the at least two wiring layers. 
     
     
         8 . The ASIC according to  claim 1 , wherein the connections between a lower wiring layer of the at least two wiring layers in a wiring zone and the first wiring layer situated underneath the lower wiring layer are formed by mask-programmable switches in an intervening insulation layer. 
     
     
         9 . The ASIC according to  claim 1 , wherein connections between at least two wiring lines of the at least two wiring layers of a wiring zone are formed by mask-programmable switches in an insulation layer situated between the at least two wiring layers. 
     
     
         10 . The ASIC according to  claim 1 , wherein connections between wiring lines of a wiring zone and wiring lines of an adjacent wiring zone within a wiring layer are formed by mask-programmable switches in the form of metal bridges. 
     
     
         11 . The ASIC according to  claim 1 , wherein connections between wiring lines of a wiring zone and wiring lines of an adjacent wiring zone within a wiring layer are formed by mask-programmable switches in the form of vias. 
     
     
         12 . The ASIC according to  claim 1 , wherein connections between wiring lines of the at least two wiring layers of a wiring zone are formed by active switches. 
     
     
         13 . The ASIC according to  claim 1 , wherein connections between wiring lines of the at least two wiring layers of a wiring zone are formed by inverting and/or non-inverting tristate buffers, pass gates, or transfer gates. 
     
     
         14 . The ASIC according to  claim 1 , wherein, wiring lines of a wiring zone are orthogonal to wiring lines of an adjacent wiring zone within a same wiring layer. 
     
     
         15 . An application-specific integrated semiconductor circuit (ASIC), comprising:
 an array of logic function blocks disposed in a substrate and in a first wiring layer, the first wiring layer at least partially defining a function of the logic function block; and   an array of wiring zones corresponding to the array of logic function blocks and disposed over the array of logic function blocks, the array of wiring zones serving for routing signals between the array of logic function blocks, the array of wiring zones comprising first line segments in the first wiring layer and second line segments disposed over the first line segments in a second wiring layer, the first and the second line segments being continuous within a wiring zone of the array of wiring zones, wherein the first and the second line segments are interrupted at boundaries between wiring zones of the array of wiring zones.   
     
     
         16 . The ASIC according to  claim 15 , wherein connections between the first and the second line segments are formed by mask-programmable switches in an insulation layer situated between the at least two wiring layers. 
     
     
         17 . The ASIC according to  claim 15 , wherein connections between the first line segments of a wiring zone and the first wiring lines of an adjacent wiring zone within the first wiring layer are formed by mask-programmable switches in the form of metal bridges. 
     
     
         18 . The ASIC according to  claim 15 , wherein connections between the first line segments of a wiring zone and the first wiring lines of an adjacent wiring zone within the first wiring layer are formed by vias. 
     
     
         19 . The ASIC according to  claim 15 , wherein connections between the first and the second line segments are formed by active switches. 
     
     
         20 . The ASIC according to  claim 15 , wherein connections between the first and the second line segments are formed by inverting and/or non-inverting tristate buffers, pass gates, or transfer gates. 
     
     
         21 . The ASIC according to  claim 15 , wherein, within a wiring layer, the first line segments of a wiring zone are orthogonal to the first line segments of an adjacent wiring zone. 
     
     
         22 . An application-specific integrated semiconductor circuit (ASIC), comprising:
 an array of logic function blocks disposed in a substrate and in a first wiring layer, the first wiring layer at least partially defining a function of the logic function block; and   an array of wiring zones corresponding to the array of logic function blocks and disposed over the array of logic function blocks, the array of wiring zones serving for routing signals between the array of logic function blocks, the array of wiring zones comprising first line segments in the first wiring layer and second line segments disposed over the first line segments in a second wiring layer, the first and the second line segments being continuous within a wiring zone of the array of wiring zones, wherein the first and the second line segments are interrupted at boundaries between wiring zones of the array of wiring zones, wherein, at a first wiring zone boundary, the first line segments of a wiring zone of the array of wiring zones are coupled to the corresponding first line segments of an adjacent wiring zone of the array of wiring zones through first mask programmable switches, wherein, at a second wiring zone boundary, the second line segments of a wiring zone of the array of wiring zones are coupled to the corresponding second line segments of an adjacent wiring zone of the array of wiring zones through second mask programmable switches, wherein each line of the first line segments is coupled to a corresponding line of the second line segments through a third mask programmable switch.   
     
     
         23 . The ASIC according to  claim 22 , wherein the first and the second mask programmable switches comprise metal bridges. 
     
     
         24 . The ASIC according to  claim 22 , wherein the first and the second mask programmable switches comprise vias. 
     
     
         25 . The ASIC according to  claim 22 , wherein the first and the second mask programmable switches comprise vias in an insulation layer between the first and the second wiring layers.