Non-volatile memory device and method for fabricating the same

Abstract

A method for fabricating a non-volatile memory device, the method includes alternately stacking inter-layer dielectric layers and sacrificial layers over a substrate, etching the inter-layer dielectric layers and the sacrificial layers to form trenches to expose a surface of the substrate, etching the inter-layer dielectric layers exposed by the trenches to a predetermined thickness, forming junction layers over etched portions of the inter-layer dielectric layers, and burying a layer for a channel within the trenches in which the junction layers have been formed to form a channel.

1 . A non-volatile memory device comprising:
 a plurality of inter-layer dielectric layers and a plurality of gate electrodes alternately stacked over a substrate;   a plurality of channels passing through the plurality of inter-layer dielectric layers and the plurality of gate electrodes and protruding from the substrate; and   a plurality of junction layers disposed between the plurality of channels and the plurality of inter-layer dielectric layers.   
     
     
         2 . The non-volatile memory device of  claim 1 , further comprising:
 a charge blocking layer, a charge trap layer, and a tunnel insulation layer disposed between the plurality of channels and the plurality of gate electrodes.   
     
     
         3 . The non-volatile memory device of  claim 1 , wherein a plurality of memory cells included in the non-volatile memory device are configured to operate in an enhancement-mode. 
     
     
         4 . The non-volatile memory device of  claim 1 , wherein the plurality of channels are doped with a P-type impurity, and the plurality of junction layers are doped with an N-type impurity. 
     
     
         5 . The non-volatile memory device of  claim 4 , wherein a doping concentration of the N-type impurity is in a range of from approximately 1E10/cm 2  to approximately 1E15/cm 2 . 
     
     
         6 . A method for fabricating a non-volatile memory device, the method comprising:
 alternately stacking a plurality of inter-layer dielectric layers and a plurality of sacrificial layers over a substrate;   etching the plurality of inter-layer dielectric layers and the plurality of sacrificial layers to form a plurality of trenches to expose a surface of the substrate;   etching the inter-layer dielectric layers exposed by the plurality of trenches to a predetermined thickness;   forming a plurality of junction layers over etched portions of the inter-layer dielectric layers; and   burying a layer within the plurality of trenches in which the plurality of junction layers have been formed to form a plurality of channels.   
     
     
         7 . The method of  claim 6 , wherein the plurality of inter-layer dielectric layers are formed of an oxide layer and the plurality of sacrificial layers are formed of a nitride layer, or the plurality of inter-layer dielectric layers are formed of a nitride layer and the plurality of sacrificial layers are formed of an oxide layer. 
     
     
         8 . The method of  claim 6 , wherein the etching of the plurality of inter-layer dielectric layers to the predetermined thickness includes performing a wet etch process. 
     
     
         9 . The method of  claim 6 , wherein the forming of the plurality of junction layers includes:
 forming a material layer for a junction over a bottom portion and an inner portion of the plurality of trenches while the etched portions of the plurality of inter-layer dielectric layers are buried; and   removing a portion of the material layer for the junction except for the material layer for the junction formed within the etched portions of the etched plurality of inter-layer dielectric layers to separate each of the junction layers.   
     
     
         10 . The method of  claim 6 , wherein the etching of the plurality of inter-layer dielectric layers to the predetermined thickness includes over-etching the plurality of inter-layer dielectric layers to be greater than a final width of the plurality of junction layers in a range of from approximately 1% to approximately 20%. 
     
     
         11 . The method of  claim 10 , wherein the forming of the plurality of junction layers includes:
 forming a material layer for a junction over a bottom portion and an inner portion of the plurality of trenches while the over-etched portions of the plurality of inter-layer dielectric layers are buried; and   removing portions of the material layer for the junction formed over the bottom portion and the inner portion of the plurality of trenches, portions of the material layer for the junction formed within the over-etched portions of the plurality of inter-layer dielectric layers, and portions of the plurality of sacrificial layers being configured to separate each of the junction layers and to determine a final width of the junction layers.   
     
     
         12 . The method of  claim 6 , further comprising:
 forming a trench for removing the plurality of sacrificial layers by partially etching the etched plurality of inter-layer dielectric layers and the plurality of sacrificial layers between the plurality of channels;   removing the plurality of sacrificial layers exposed by the trench for removing the plurality of sacrificial layers;   forming a charge blocking layer, a charge trap layer, and a tunnel insulation layer over a resultant structure in which the plurality of sacrificial layers have been removed; and   forming gate electrodes over the resultant structure in which the charge blocking layer, the charge trap layer, and the tunnel insulation layer have been formed.   
     
     
         13 . The method of  claim 12 , wherein the trench for removing the plurality of sacrificial layers includes a line-type trench. 
     
     
         14 . A method for fabricating a non-volatile memory device, the method comprising:
 forming a well region over a substrate;   forming a common source region within the well region;   alternately stacking a plurality of inter-layer dielectric layers and a plurality of conductive layers over the substrate having the common source region;   etching the plurality of inter-layer dielectric layers and the plurality of conductive layers to form a trench to expose a surface of the substrate;   forming a pickup region over the well region by doping an impurity into the substrate exposed by the trench; and   burying a layer for a channel within the trench to form a channel.   
     
     
         15 . The method of  claim 14 , further comprising forming source/drain regions inside the channel on both sides of each of the plurality of inter-layer dielectric layers. 
     
     
         16 . The method of  claim 14 , further comprising forming a charge blocking layer, a charge trap layer, and a tunnel insulation layer on an inner wall of the trench. 
     
     
         17 . The method of  claim 16 , further comprising forming a spacer over the charge blocking layer, the charge trap layer, and the tunnel insulation layer. 
     
     
         18 . The method of  claim 17 , wherein forming the spacer comprises forming one of a nitride layer, a carbon layer, and a conductive layer. 
     
     
         19 . The method of  claim 18 , wherein forming the conductive layer includes forming a polysilicon layer. 
     
     
         20 . The method of  claim 14 , wherein a width of the pickup region is formed to be smaller than a width of the channel. 
     
     
         21 . The method of  claim 14 , wherein the well region is formed to have a same conductive-type as that of the pickup region and the channel. 
     
     
         22 . The method of  claim 21 , wherein the well region is formed to have a different conductive-type than that of the common source region. 
     
     
         23 . The method of  claim 21 , further comprising electrically connecting the channel to the well region through the pickup region. 
     
     
         24 . The method of  claim 14 , wherein a plurality of memory cells included in the non-volatile memory device are configured to operate in an enhancement-mode. 
     
     
         25 . A non-volatile memory device comprising:
 a plurality of memory cells stacked along a channel vertically protruding from a substrate;   a well region arranged in the substrate;   a common source region arranged within the well region; and   a pickup region arranged in the substrate to connect the channel to the well region.   
     
     
         26 . The non-volatile memory device of  claim 25 , wherein the plurality of memory cells are configured to operate in an enhancement-mode. 
     
     
         27 . The non-volatile memory device of  claim 25 , wherein a width of the pickup region is smaller than a width of the channel. 
     
     
         28 . The non-volatile memory device of  claim 25 , wherein a conductive-type of the well region is the same as that of the pickup region and the channel. 
     
     
         29 . The non-volatile memory device of  claim 28 , wherein the conductive-type of the well region is different from that of the common source region. 
     
     
         30 . The non-volatile memory device of  claim 25 , wherein the channel is electrically connected to the well region through the pickup region.