Method for improving the thermal stability of silicide

Abstract

An embodiment of the invention is a method of making a transistor by performing an ion implant on a gate electrode layer 110. The method may include forming an interface layer 200 over the semiconductor substrate 20 and performing an anneal to create a silicide 190 on the top surface of the gate electrode 110.

1 . A method for making a transistor, comprising:
 providing a semiconductor substrate;   forming a gate dielectric layer over said semiconductor substrate;   forming a gate electrode layer over said gate dielectric layer;   performing an ion implant on said gate electrode layer using N 2   +  gas; and   etching said implanted gate electrode layer and said gate dielectric layer to form a gate stack having a gate electrode and a gate dielectric.   
     
     
         2 . The method of  claim 1  further comprising:
 forming extension sidewalls coupled to said gate stack;   implanting extension regions within a top surface of said semiconductor substrate;   forming source/drain sidewalls coupled to said extension sidewalls;   implanting source/drain regions within a top surface of said semiconductor substrate;   annealing said semiconductor substrate;   forming an interface layer over said semiconductor substrate; and   performing an anneal to create a silicide within a top surface of said gate electrode.   
     
     
         3 . The method of  claim 1  wherein said gate electrode layer comprises polycrystalline silicon. 
     
     
         4 . The method of  claim 1  wherein said gate electrode layer comprises amorphous silicon. 
     
     
         5 . The method of  claim 1  wherein said transistor is a CMOS transistor. 
     
     
         6 . A method for making a transistor, comprising:
 providing a semiconductor substrate;   forming a gate dielectric layer over said semiconductor substrate;   forming a gate electrode layer over said gate dielectric layer;   performing an ion implant on said gate electrode layer using F +  gas; and   etching said implanted gate electrode layer and said gate dielectric layer to form a gate stack having a gate electrode and a gate dielectric.   
     
     
         7 . The method of  claim 6  further comprising:
 forming extension sidewalls coupled to said gate stack;   implanting extension regions within a top surface of said semiconductor substrate;   forming source/drain sidewalls coupled to said extension sidewalls;   implanting source/drain regions within a top surface of said semiconductor substrate;   annealing said semiconductor substrate;   forming an interface layer over said semiconductor substrate; and   performing an anneal to create a silicide within a top surface of said gate electrode.   
     
     
         8 . The method of  claim 6  wherein said gate electrode layer comprises polycrystalline silicon. 
     
     
         9 . The method of  claim 6  wherein said gate electrode layer comprises amorphous silicon. 
     
     
         10 . The method of  claim 6  wherein said transistor is a CMOS transistor. 
     
     
         11 . A method for making a transistor, comprising:
 providing a semiconductor substrate;   forming a gate dielectric layer over said semiconductor substrate;   forming a gate electrode layer over said gate dielectric layer;   performing an ion implant on said gate electrode layer using Sb +  gas; and   etching said implanted gate electrode layer and said gate dielectric layer to form a gate stack having a gate electrode and a gate dielectric.   
     
     
         12 . The method of  claim 11  further comprising:
 forming extension sidewalls coupled to said gate stack;   implanting extension regions within a top surface of said semiconductor substrate;   forming source/drain sidewalls coupled to said extension sidewalls;   implanting source/drain regions within a top surface of said semiconductor substrate;   annealing said semiconductor substrate;   forming an interface layer over said semiconductor substrate; and   performing an anneal to create a silicide within a top surface of said gate electrode.   
     
     
         13 . The method of  claim 11  wherein said gate electrode layer comprises polycrystalline silicon. 
     
     
         14 . The method of  claim 11  wherein said gate electrode layer comprises amorphous silicon. 
     
     
         15 . The method of  claim 11  wherein said transistor is a CMOS transistor.