Method and apparatus for increasing load bandwidth

Abstract

A method and apparatus for dual-target register allocation is described, intended to enable the efficient mapping/renaming of registers associated with instructions within a pipelined microprocessor architecture.

1 - 34 . (canceled) 
     
     
         35 . A method comprising:
 scheduling a plurality of load operations to be performed within a load cycle, said plurality of load operations comprising a load operation predicted to be satisfied by accessing a store-forwarding buffer; and   issuing a load operation predicted to be satisfied by accessing said store-forwarding buffer to the store-forwarding buffer and not a data load cache.   
     
     
         36 . The method of  claim 35  further comprising issuing a load operation not predicted to be satisfied by accessing said store-forwarding buffer to the data load cache within said load cycle. 
     
     
         37 . The method of  claim 35  further comprising issuing said load operation to said data load cache if the load operation is not predicted to be satisfied by accessing the store-forwarding buffer. 
     
     
         38 . The method of  claim 35  wherein said predicting is a function of how often said load operation is satisfied by accessing a store-forwarding buffer. 
     
     
         39 . An apparatus comprising:
 a prediction unit to predict whether a load operation will be satisfied by accessing a store-forwarding buffer,   wherein said load operation predicted to be satisfied by accessing said store-forwarding buffer is to be issued to said store-forwarding buffer and not a data load cache unit if no other load operation has been issued to said data load cache unit within a load cycle.   
     
     
         40 . The apparatus of  claim 39  wherein the scheduler unit is to schedule a plurality of load operations within a load cycle, wherein said scheduler unit is enabled to schedule a load operation not predicted to be satisfied by accessing said store-forwarding buffer within said load cycle. 
     
     
         41 . The apparatus of  claim 40  wherein said load operation not predicted to be satisfied by accessing said store-forwarding buffer is issued to a data cache unit. 
     
     
         42 . The apparatus of  claim 41  wherein said load operation not predicted to be satisfied by accessing said store-forwarding buffer is issued to said store-forwarding buffer within said load cycle. 
     
     
         43 . The apparatus of  claim 42 , wherein said plurality of load operations comprises a load operation predicted by said prediction unit to be satisfied by accessing said store-forwarding buffer. 
     
     
         44 . The apparatus of  claim 42  wherein said load operation predicted to be satisfied by accessing said store-forwarding buffer or said load operation not predicted to be satisfied by accessing said store-forwarding buffer is rescheduled if said prediction is incorrect. 
     
     
         45 . The apparatus of  claim 44  wherein said rescheduling comprises rescheduling a dependent load operation, said dependent load operation being dependent upon said load operation predicted to be satisfied by accessing said store-forwarding buffer or upon said load operation not predicted to be satisfied by accessing said store-forwarding buffer. 
     
     
         46 . The apparatus of  claim 39  further comprising a store buffer, said prediction unit being coupled to said store buffer. 
     
     
         47 . The apparatus of  claim 46  wherein said predicting is a function of how often load operation is satisfied by accessing a store-forwarding buffer. 
     
     
         48 . The apparatus of  claim 47  wherein said function is dependent upon whether said load operation predicted to be satisfied by accessing said store-forwarding buffer is present within said store buffer. 
     
     
         49 . A system comprising:
 a prediction unit to predict whether a load operation will be satisfied by accessing a store-forwarding buffer;   a scheduler unit to schedule a plurality of load operations within a load cycle, said plurality of load operations comprising a load operation predicted by said prediction unit to be satisfied by accessing said store-forwarding buffer,   wherein the load operation is issued to a data load cache unit and not the store-forwarding buffer if the load operations is not predicted to be satisfied by accessing said store-forwarding buffer.   
     
     
         50 . The system of  claim 49  wherein said scheduler unit is enabled to schedule a load operation not predicted to be satisfied by accessing said store-forwarding buffer within said load cycle. 
     
     
         51 . The system of  claim 50  wherein said load operation not predicted to be satisfied by accessing said store-forwarding buffer is issued to said data load cache unit. 
     
     
         52 . The system of  claim 51  wherein said load operation not predicted to be satisfied by accessing said store-forwarding buffer is issued to said store-forwarding buffer within said load cycle. 
     
     
         53 . The system of  claim 52  wherein said load operation predicted to be satisfied by accessing said store-forwarding buffer or said load operation not predicted to be satisfied by accessing said store-forwarding buffer is rescheduled if said prediction is incorrect.