Chip-type electric double layer capacitor and method of manufacturing the same

Abstract

A chip-type electric double layer capacitor includes: an exterior case including a housing space formed therein and formed of insulation resin; a first external terminal buried in the exterior case and including a first surface exposed to the housing space and a second surface exposed to the outside of the exterior case; a second external terminal buried in the exterior case and including a first surface exposed to the housing space and a second surface exposed to the outside of the exterior case; and an electric double layer cell disposed in the housing space so as to be electrically connected to the first surfaces of the first and second external terminals.

1 . A chip-type electric double layer capacitor comprising:
 an exterior case comprising a housing space formed therein and formed of insulation resin;   a first external terminal buried in the exterior case and comprising a first surface exposed to the housing space and a second surface exposed to the outside of the exterior case;   a second external terminal buried in the exterior case and comprising a first surface exposed to the housing space and a second surface exposed to the outside of the exterior case; and   an electric double layer cell disposed in the housing space so as to be electrically connected to the first surfaces of the first and second external terminals.   
     
     
         2 . The chip-type electric double layer capacitor of  claim 1 , wherein the first and second external terminals are buried in the external case by insert injection molding. 
     
     
         3 . The chip-type electric double layer capacitor of  claim 1 , wherein the first and second external terminals have a buried region extension region. 
     
     
         4 . The chip-type electric double layer capacitor of  claim 1 , wherein the insulation resin is polyphenylene sulfide (PPS) or liquid crystal polymer (LCP). 
     
     
         5 . The chip-type electric double layer capacitor of  claim 1 , further comprising adhesive layers which are formed to cover boundary surfaces between the exterior case and the first and second external terminals, respectively. 
     
     
         6 . The chip-type electric double layer capacitor of  claim 5 , wherein the adhesive layers are formed to cover boundary surfaces between the exterior case and the second surfaces of the first and second external terminals, respectively. 
     
     
         7 . The chip-type electric double layer capacitor of  claim 5 , wherein the adhesive layers are formed to cover boundary surfaces between the exterior case and the first surfaces of the first and second external terminals, respectively. 
     
     
         8 . The chip-type electric double layer capacitor of  claim 5 , wherein the adhesive layers comprise epoxy resin. 
     
     
         9 . The chip-type electric double layer capacitor of  claim 1 , wherein the first and second external terminals are formed on the same surface of the exterior case. 
     
     
         10 . The chip-type electric double layer capacitor of  claim 1 , wherein the first and second external terminals are formed at both ends of the same surface of the exterior case. 
     
     
         11 . The chip-type electric double layer capacitor of  claim 1 , wherein the first and second external terminals are formed on the same surface of the exterior case so as to be positioned toward the central portion of the surface. 
     
     
         12 . The chip-type electric double layer capacitor of  claim 1 , wherein the exterior case further comprises sealing portions formed in the respective corners of the housing space. 
     
     
         13 . The chip-type electric double layer capacitor of  claim 1 , wherein the exterior case comprises:
 a lower case having the housing space of which the top surface is opened and the first and second external terminals buried therein; and   an upper cap mounted on the lower case so as to cover the housing space.   
     
     
         14 . The chip-type electric double layer capacitor of  claim 1 , wherein the exterior case comprises:
 a lower case having the housing space of which the top surface is opened, sealing portions formed in the corner of the respective corners of the housing space, and the first and second external terminals buried therein; and   an upper cap mounted on the lower case having the sealing portions so as to cover the housing space.   
     
     
         15 . The chip-type electric double layer capacitor of  claim 13 , wherein the lower case and the upper cap are coupled to each other by welding or ultrasonic welding. 
     
     
         16 . The chip-type electric double layer capacitor of  claim 14 , wherein the sealing portions are formed integrally with the lower case by insert injection molding. 
     
     
         17 . The chip-type electric double layer capacitor of  claim 14 , wherein the sealing portions are formed separately from the lower case by double injection molding. 
     
     
         18 . The chip-type electric double layer capacitor of  claim 14 , wherein the sealing portions and the lower case are formed of the same insulation resin or different insulation resins. 
     
     
         19 . The chip-type electric double layer capacitor of  claim 1 , wherein the electric double layer capacitor cell comprises first and second current collectors, first and second electrodes connected to the first and second current collectors, respectively, and an ion-permeable separator formed between the first and second electrodes. 
     
     
         20 . The chip-type electric double layer capacitor of  claim 1 , wherein the first surfaces of the first and second external terminals and the electric double layer capacitor cell are connected by welding or ultrasonic welding. 
     
     
         21 . The chip-type electric double layer capacitor of  claim 1 , wherein the electric double layer capacitor cell comprises one or more pairs of first and second current collectors, one or more pairs of first and second electrodes, and one or more separators which are continuously stacked. 
     
     
         22 . The chip-type electric double layer capacitor of  claim 1 , wherein the electric double layer capacitor cell is formed by winding first and second electrodes. 
     
     
         23 . A method of manufacturing a chip-type electric double layer capacitor, comprising:
 forming a lower case having an opened housing space and first and second external terminals buried therein, the first and second external terminals having first surfaces exposed to the housing space, respectively, and second surfaces exposed to an outer region of the lower case, respectively;   mounting an electric double layer capacitor cell in the housing space such that the electric double layer capacitor cell is electrically connected to the first surfaces of the first and second external terminals exposed to the housing space; and   mounting an upper cap on the lower case so as to cover the housing space.   
     
     
         24 . The method of  claim 23 , further comprising forming adhesive layers to cover boundary surfaces between the exterior case and the first and second external terminals. 
     
     
         25 . The method of  claim 23 , wherein the forming of the lower case is performed by insert injection molding. 
     
     
         26 . The method of  claim 23 , further comprising forming sealing portions in the respective corners of the housing space. 
     
     
         27 . The method of  claim 26 , wherein the sealing portions are formed integrally with the lower case by insert injection molding. 
     
     
         28 . The method of  claim 26 , wherein the sealing portions are formed separately from the lower case by double injection molding. 
     
     
         29 . The method of  claim 23 , wherein the connection between the first and second external terminals and the electric double layer capacitor cell is performed by welding or ultrasonic welding. 
     
     
         30 . The method of  claim 23 , wherein the mounting of the upper cap on the lower case is performed by welding or ultrasonic welding.