Frequency doubling using spacer mask

Abstract

A method for fabricating a semiconductor mask is described. A semiconductor stack having a sacrificial mask and a spacer mask is first provided. The sacrificial mask is comprised of a series of lines and the spacer mask has spacer lines adjacent to the sidewalls of the series of lines. Next, the spacer mask is cropped. Finally, the sacrificial mask is removed to provide a cropped spacer mask. The cropped spacer mask doubles the frequency of the series of lines of the sacrificial mask.

1 . A method for fabricating a semiconductor mask, comprising:
 providing a semiconductor stack having thereon a sacrificial mask and a spacer mask, wherein said sacrificial mask comprises a series of lines, and wherein said spacer mask comprises spacer lines adjacent to the sidewalls of said series of lines as well as one or more area-preservation regions;   removing said sacrificial mask; and, subsequently,   cropping said spacer lines of said spacer mask.   
     
     
         2 . The method of  claim 1  wherein the frequency of said spacer lines is double the frequency of said series of lines of said sacrificial mask. 
     
     
         3 . The method of  claim 2  wherein the pitch of said series of lines of said sacrificial mask is approximately 4. 
     
     
         4 . A method for fabricating a semiconductor mask, comprising:
 providing a semiconductor stack having a mask layer;   depositing and patterning a first photoresist layer to form an image above said mask layer;   etching said mask layer to form a sacrificial mask having said image, wherein said sacrificial mask is comprised of a series of lines;   depositing a spacer layer above said semiconductor stack and conformal with said sacrificial mask;   depositing and patterning a second photoresist layer to form an area-preservation mask above said spacer layer;   etching said spacer layer to provide a spacer mask comprised of spacer regions and area-preservation regions, wherein the spacer regions are adjacent to the sidewalls of said series of lines of said sacrificial mask, and wherein etching said spacer layer exposes the top surface of said sacrificial mask;   depositing and patterning a third photoresist layer above said spacer mask and said sacrificial mask to expose at least a portion of the spacer regions of said spacer mask;   etching the exposed portion of the spacer regions of said spacer mask to crop said spacer mask; and   removing said sacrificial mask.   
     
     
         5 . The method of  claim 4  wherein said spacer layer is comprised substantially of silicon, wherein the top portion of said sacrificial mask is comprised substantially of a material selected from the group consisting of silicon nitride and silicon oxide, and wherein etching said spacer layer to provide said spacer mask comprises using a dry etch process with a gas selected from the group consisting of Cl 2  and HBr. 
     
     
         6 . The method of  claim 5  wherein removing said sacrificial mask comprises using an etch process selected from the group consisting of a hot H 3 PO 4  wet etch, an aqueous hydrofluoric acid wet etch and a SiCoNi etch. 
     
     
         7 . The method of  claim 4  wherein said spacer layer is comprised substantially of silicon oxide, wherein the top portion of said sacrificial mask is comprised substantially of a material selected from the group consisting of silicon nitride and silicon, and wherein etching said spacer layer to provide said spacer mask comprises using a dry etch process with a gas selected from the group consisting of C 4 F 8  and CHF 3 . 
     
     
         8 . The method of  claim 7  wherein removing said sacrificial mask comprises using an etch process selected from the group consisting of a hot H 3 PO 4  wet etch, a SiCoNi etch, a Cl 2  plasma etch and a CF 4 /O 2  plasma etch. 
     
     
         9 . A method for fabricating a semiconductor mask, comprising:
 providing a semiconductor stack having a mask layer;   depositing and patterning a first photoresist layer to form an image above said mask layer;   etching said mask layer to form a sacrificial mask having said image, wherein said sacrificial mask is comprised of a series of lines;   depositing a spacer layer above said semiconductor stack and conformal with said sacrificial mask;   depositing and patterning a second photoresist layer above said spacer layer and said sacrificial mask to expose at least a portion of the spacer regions of said spacer layer;   etching the exposed portion of the spacer regions of said spacer layer to form a cropped spacer layer;   depositing and patterning a third photoresist layer to form an area-preservation mask above said cropped spacer layer;   etching said cropped spacer layer to provide a spacer mask comprised of spacer regions and area-preservation regions, wherein the spacer regions are adjacent to the sidewalls of said series of lines of said sacrificial mask, and wherein etching said cropped spacer layer exposes the top surface of said sacrificial mask; and   removing said sacrificial mask.   
     
     
         10 . The method of  claim 9  wherein said spacer layer is comprised substantially of silicon, wherein the top portion of said sacrificial mask is comprised substantially of a material selected from the group consisting of silicon nitride and silicon oxide, and wherein etching said spacer layer to provide said spacer mask comprises using a dry etch process with a gas selected from the group consisting of Cl 2  and HBr. 
     
     
         11 . The method of  claim 10  wherein removing said sacrificial mask comprises using an etch process selected from the group consisting of a hot H 3 PO 4  wet etch, an aqueous hydrofluoric acid wet etch and a SiCoNi etch. 
     
     
         12 . The method of  claim 9  wherein said spacer layer is comprised substantially of silicon oxide, wherein the top portion of said sacrificial mask is comprised substantially of a material selected from the group consisting of silicon nitride and silicon, and wherein etching said spacer layer to provide said spacer mask comprises using a dry etch process with a gas selected from the group consisting of C 4 F 8  and CHF 3 . 
     
     
         13 . The method of  claim 12  wherein removing said sacrificial mask comprises using an etch process selected from the group consisting of a hot H 3 PO 4  wet etch, a SiCoNi etch, a Cl 2  plasma etch and a CF 4 /O 2  plasma etch. 
     
     
         14 . The method of  claim 9  wherein said spacer layer is comprised substantially of silicon nitride, wherein the top portion of said sacrificial mask is comprised substantially of a material selected from the group consisting of silicon oxide and silicon, and wherein etching said spacer layer to provide said spacer mask comprises using a dry etch process with a gas selected from the group consisting of CH 2 F 2  and CHF 3 . 
     
     
         15 . The method of  claim 14  wherein removing said sacrificial mask comprises using an etch process selected from the group consisting of an aqueous hydrofluoric acid wet etch, a SiCoNi etch, a Cl 2  plasma etch and a CF 4 /O 2  plasma etch.