Method of manufacture of contact plug and interconnection layer of semiconductor device

Abstract

A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas.

1 . A semiconductor device comprising:
 a semiconductor substrate having a first surface;   two first gate electrodes disposed along a first direction on the first surface;   first source/drain areas formed in the first surface and sandwiching a first channel region under each of the first gate electrodes;   a first interlayer insulating layer filling a region between the two first gate electrodes and having a top lower in level than a top of each of the first gate electrodes;   a second interlayer insulating layer disposed above the first gate electrodes and the first interlayer insulating layer;   a first interconnect layer disposed in the second interlayer insulating layer along a direction which intersects the first direction; and disposed on one of the two first gate electrodes; and   a first contact plug formed in the first interlayer insulating layer and the second interlayer insulating layer and being in contact with one of the interconnect layers and one of the first source/drain areas and being in contact with the first interconnect layer.   
     
     
         2 . The device according to  claim 1 , wherein a top of one of the first gate electrodes is formed from a metal compound. 
     
     
         3 . The device according to  claim 2 , wherein the first interlayer insulating layer having an insulating layer and a first barrier layer and a second barrier layer, and one of the barrier layers formed between the first surface and the second interlayer insulating layer and/or between a first sidewall of one of the first gate electrodes and the first interlayer insulating layer. 
     
     
         4 . The device according to  claim 3 , further comprising a second gate electrode disposed on the first surface and covered by the first interlayer insulating layer. 
     
     
         5 . The device according to  claim 4 , wherein a top of the second gate electrode is different in material from the top of one of the first gate electrodes. 
     
     
         6 . The device according to  claim 1 , further comprising
 a second gate electrode formed on the first surface; and   a third interlayer insulating layer filling a region between one of the two first gate electrodes and the second gate electrode, having a top higher in level than the top of the first interlayer insulating layer, and being formed from a material different in etching rate from a material forming the first interlayer insulating layer.   
     
     
         7 . The device according to  claim 1 , wherein the first contact plug comprises a first portion which is located in the first interlayer insulating layer and a second portion which is located in the second interlayer insulating layer and is larger in size in a plane parallel to the first surface than the first portion. 
     
     
         8 . The device according to  claim 7 , wherein a top of one of the first gate electrodes is formed from a metal compound. 
     
     
         9 . The device according to  claim 8 , wherein the first interlayer insulating layer having an insulating layer and a first barrier layer and a second barrier layer, and one of the barrier layers formed between the first surface and the second interlayer insulating layer and/or between a first sidewall of one of the first gate electrodes and the first interlayer insulating layer. 
     
     
         10 . The device according to  claim 9 , further comprising a second gate electrode disposed on the first surface and covered by the first interlayer insulating layer. 
     
     
         11 . The device according to  claim 10 , wherein a top of the second gate electrode is different in material from the top of one of the first gate electrodes. 
     
     
         12 . The device according to  claim 7 , further comprising
 a second gate electrode disposed on the first surface; and   a third interlayer insulating layer filling a region between one of the first gate electrode and the second gate electrode, having a top higher in level than the top of the first interlayer insulating layer, and being formed from a material different in etching rate from a material forming the first interlayer insulating layer.   
     
     
         13 . The device according to  claim 3 , wherein the second barrier layer formed between the two first gate electrodes and the second interlayer insulating layer, and formed between the second gate electrodes and the third interlayer insulating layer. 
     
     
         14 . The device according to  claim 9 , wherein the second barrier layer formed between the two first gate electrodes and the second interlayer insulating layer and formed between the second gate electrodes and the third interlayer insulating layer. 
     
     
         15 . The device according to  claim 3 , wherein
 the first barrier layer has a concave shape,   the two first gate electrodes have an integrate insulating layer,   a top of the first barrier layer is equal to a top of the insulating layer, and   the top of the first interlayer insulating layer is higher than the integrate insulating layer.   
     
     
         16 . The device according to  claim 9 , wherein
 the first barrier layer has a concave shape,   the two first gate electrodes have an integrate insulating layer,   a top of the first barrier layer is equal to a top of the insulating layer, and   the top of the first interlayer insulating layer is higher than the integrate insulating layer.   
     
     
         17 . The device according to  claim 1 , wherein
 the first interconnect layer is an interconnect layer which is disposed on one of the two first gate electrodes.