Non-linear conductor memory

Abstract

A high-speed, low-power memory device comprises an array of non-linear conductors wherein the storage, address decoding, and output detection are all accomplished with diodes or other non-linear conductors. In various embodiments, the row and column resistors are switchable between a high resistance when connected to a row or column that is non-selected, and a low resistance when connected to the selected row and column.

1 - 23 . (canceled) 
     
     
         24 . A system for storing and retrieving digital information, the system comprising:
 a first array of nonlinear conductive devices for information storage therein and retrieval therefrom, each device being addressable by one of a plurality of row lines and one of a plurality of column lines;   a plurality of row switches, each row switch providing a variable-impedance connection between one of the plurality of row lines and a row voltage source; and   a row-address decoder for selecting, using a second array of nonlinear conductive devices, one of the plurality of row switches, thereby causing an impedance of the selected row switch to be lower than impedances of the non-selected row switches.   
     
     
         25 . The system of  claim 24 , further comprising an internal row-address decoder for clamping, using a fourth array of nonlinear conductive devices, voltages of the non-selected row lines. 
     
     
         26 . The system of  claim 24 , further comprising:
 a plurality of column switches, each column switch providing a variable-impedance connection between one of the plurality of column lines and a column voltage source; and   a column-address decoder for selecting, using a third array of nonlinear conductive devices, one of the plurality of column switches, thereby causing an impedance of the selected column switch to be lower than impedances of the non-selected column switches.   
     
     
         27 . The system of  claim 26 , further comprising an internal column-address decoder for clamping, using a fourth array of nonlinear conductive devices, voltages of the non-selected column lines. 
     
     
         28 . The system of  claim 24 , wherein the row and column switches are disposed in a first layer and the first array of nonlinear conductive devices is disposed in a second layer. 
     
     
         29 . The system of  claim 24 , wherein the first array of nonlinear conductive devices comprises a plurality of sub-arrays simultaneously addressable by the row and column lines. 
     
     
         30 . The system of  claim 29 , wherein the sub-arrays are tiled. 
     
     
         31 . The system of  claim 24 , wherein the nonlinear conductive devices comprise at least one of a diode, a fuse, an antifuse, a phase-change material, a resistance-change material, or a chalcogenide material. 
     
     
         32 . The system of  claim 24 , wherein a first row switch comprises an enhancement-mode transistor, a depletion-mode transistor, an NMOS transistor, a PMOS transistor, or a bipolar transistor. 
     
     
         33 . The system of  claim 32 , wherein a second row switch comprises an enhancement-mode transistor, a depletion-mode transistor, an NMOS transistor, a PMOS transistor, or a bipolar transistor, and wherein the second row switch is a device different from the first row switch. 
     
     
         34 . A method for addressing a first array of nonlinear conductive devices, the method comprising:
 decoding, using a second array of nonlinear conductive devices, a row address;   selecting, using the decoded row address, one of a plurality of row switches, thereby causing the selected row switch to have an impedance lower than impedances of non-selected row switches;   applying, using the selected row switch, a row voltage to one of a plurality of row lines, thereby selecting one of a plurality of rows in the first array of nonlinear conductive devices for reading or writing.   
     
     
         35 . The method of  claim 34 , further comprising:
 decoding, using a third array of nonlinear conductive devices, a column address;   selecting, using the decoded column address, one of a plurality of column switches, thereby causing the selected column switch to have an impedance lower than impedances of non-selected column switches;   applying, using the selected column switch, a column voltage to one of a plurality of column lines, thereby selecting one of a plurality of columns in the first array of nonlinear conductive devices for reading or writing.   
     
     
         36 . The method of  claim 35 , further comprising retaining the selected row line and selecting a new column line. 
     
     
         37 . The method of  claim 34 , further comprising changing a state of a nonlinear conductive device in the first array by applying the row voltage, the nonlinear conductive device being in electrical communication with the selected row line and a selected column line. 
     
     
         38 . The method of  claim 37 , wherein changing the state of the nonlinear conductive device comprises applying a write pulse having a duration of less than one microsecond thereto. 
     
     
         39 . The method of  claim 34 , further comprising detecting a state of a nonlinear conductive device in the first array by applying the row voltage, the nonlinear conductive device being in electrical communication with the selected row line and a selected column line. 
     
     
         40 . The method of  claim 34 , further comprising detecting a state of each of a plurality of nonlinear conductive devices in the first array by applying the row voltage, the plurality of nonlinear conductive devices being in electrical communication with the selected row line. 
     
     
         41 . The method of  claim 34 , further comprising applying, prior to selecting one of the plurality of row switches, a pre-charge voltage to each of the plurality of row switches. 
     
     
         42 . The method of  claim 34 , further comprising reading a complimentary bit output from the first array of nonlinear conductive devices. 
     
     
         43 . The method of  claim 34 , wherein each of the plurality of row lines are complementary. 
     
     
         44 . The method of  claim 34 , wherein the row voltage is one of a read voltage or a write voltage. 
     
     
         45 . A digital memory device comprising:
 an input port for receiving a memory address;   row and column address decoders for decoding the memory address, each address decoder comprising a decoder array of nonlinear conductive devices;   a plurality of row switches for causing, based on the decoded memory address, an impedance of a selected row switch to be lower than impedances of the non-selected row switches, thereby selecting one of a plurality of row lines connected thereto;   a plurality of column switches for causing, based on the decoded memory address, an impedance of a selected column switch to be lower than impedances of the non-selected column switches, thereby selecting one of a plurality of column lines connected thereto;   an storage array of nonlinear conductive devices, each device being addressable by one of the plurality of row lines and one of the plurality of column lines; and   an input/output port for accessing data stored at the selected row and column lines corresponding to the memory address.   
     
     
         46 . The device of  claim 45 , wherein the device is compatible with the interface standard for at least one of Compact Flash data, Secure Digital data, USB memory stick data, or PCMCIA data. 
     
     
         47 . The device of  claim 45 , wherein the device comprises one of a ball-grid array, dual-in-line package, SOIC, PLCC, or TQFP. 
     
     
         48 . The device of  claim 45 , wherein the device is embedded in a memory chip, processor, PLD, PLA, microcontroller, or chipset.