Method for Specifying Stateful, Transaction-Oriented Systems for Flexible Mapping to Structurally Configurable In-Memory Processing Semiconductor Device

Abstract

A method for specifying stateful, transaction-oriented systems is provided. The method initiates with designating a plurality of primitive FlowModules. The method includes defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interruptible sequence of procedure code, a single point of entry and is invoked by a named concurrent call. An Arc is designated from a calling FlowGate to a called FlowGate and a Signal is generated for each named invocation of the called FlowGate. A Channel is defined for carrying the Signal. Methods for synthesizing a semiconductor device and routing signals in the semiconductor device are provided.

1 . A method for synthesizing a stateful, transaction-oriented system for flexible mapping to a structurally field-configurable semiconductor device having a multi-level array of storage elements, for in-memory processing, comprising method operations of:
 mapping FlowLogic to a network of FlowVirtualMachines(FVM);   mapping a FlowModule into a corresponding FlowVirtualMachine (FVM);   integrating one or more FVMs into an AggregateFVM (AFVM);   composing one or more AFVMs into a FlowTile, and   routing Signals between FlowModules.   
     
     
         2 . The method of  claim 1 , wherein the FVM is an array of similar memory unit resources configured into partitions, the partitions accessible via a plurality of independent access paths. 
     
     
         3 . The method of  claim 1  wherein the partitions define a FlowGateIndex, a StackMemory space, a CodeMemory space, a StateMemory space, an OutputBuffer space and a ChannelMemory space. 
     
     
         4 . The method of  claim 2 , further comprising:
 relocating the partitions; and   repeating the method operations of mapping FlowLogic to a network of FlowVirtualMachines(FVM);
 mapping a FlowModule into a corresponding FlowVirtualMachine (FVM); 
 integrating one or more FVMs into an AggregateFVM (AFVM); 
 composing one or more AFVMs into a FlowTile, and 
 routing Signals between FlowModules. 
   
     
     
         5 . The method of  claim 1  wherein the AFVM is derived from a composition of FVMs by one of linearly aggregating, merging or sharing memory unit resources of the composition of FVMs. 
     
     
         6 . The method of  claim 1 , wherein the FlowTile is derived from a composition of AFVMs by one of linearly aggregating, merging or sharing of the memory unit resources of the composition of AFVMs. 
     
     
         7 . The method of  claim 1 , wherein the Flowtile provides scheduling functionality through run-time flow control, reception of Signals and invoking of appropriate FlowGates. 
     
     
         8 . The method of  claim 3 , wherein the FlowTile enables signals to be commuted out of the OutputBuffer space and into the ChannelMemory space. 
     
     
         9 . The method of  claim 2 , wherein the FVM is without memory or caching hierarchies, and wherein all elements in the partitions are accessible in a same access time, the method further comprising:
 allocating and defining initial contents for all memories at compile time.   
     
     
         10 . The method of  claim 1 , further comprising:
 designating SystemFlowGates that are application independent, built-in and available on power-on boot;   providing access to the storage elements for read, write and configuration operations; and   providing booting application specific FVMs.   
     
     
         11 . The method of  claim 1 , further comprising:
 splitting the Signals into two portions, a first portion defining header information and a second portion defining a payload, the first portion residing in a different part of the memory from the second portion.   
     
     
         12 . A method for routing FlowLogic Signals over a structurally configurable in-memory processing array, the method comprising:
 configuring a pool of memory resource units into corresponding OutputBuffers, CommuteBuffers and ChannelMemories, the pool of memory units shared with a FlowLogicMachine;   configuring a producer-consumer relationship between the corresponding OutputBuffers and CommuteBuffers,   configuring a producer-consumer relationship between the CommuteBuffers and VirtualChannels residing in the ChannelMemories;   configuring producer-consumer relationships between the OutputBuffers and VirtualChannels residing in said ChannelMemories;   configuring producer-consumer relationships between the CommuteBuffers and neighbouring CommuteBuffers.   
     
     
         13 . The method of  claim 12  wherein configuring a producer-consumer relationship between the corresponding OutputBuffers and CommuteBuffers includes,
 enabling simultaneous access of the memory resource units through independent ports, asynchronous clocks and physical addressing; and 
 segmenting signals into small fixed size entities (Flits). 
 
     
     
         14 . The method of  claim 12  wherein configuring producer-consumer relationship between the CommuteBuffers and VirtualChannels residing in the ChannelMemories includes,
 enabling simultaneous access of the memory resource units through independent ports, asynchronous clocks and physical addressing; 
 reassembling the small fixed size entities in the VirtualChannels; 
 segregating small fixed size entities arriving simultaneously for different signals from different sources prior to the reassembling. 
 
     
     
         15 . The method of  claim 14 , wherein physically addressed writes into corresponding memory units achieve the reassembling and the segregating. 
     
     
         16 . The method of  claim 12  wherein configuring a producer-consumer relationship between the OutputBuffers and VirtualChannels includes,
 enabling simultaneous access of the memory resource units through independent ports, asynchronous clocks and physical addressing; 
 reassembling Flits into Signals in the VirtualChannels; and 
 segregating Flits arriving simultaneously for different Signals from different sources prior to reassembly, wherein the reassembling and the segregating are achieved through physically addressed writes into corresponding memory units. 
 
     
     
         17 . The method of  claim 12 , wherein the method operation of configuring producer-consumer relationships between the CommuteBuffers and neighbouring CommuteBuffers includes,
 enabling simultaneous access of the memory resource units through independent ports, asynchronous clocks and physical addressing; and   switching an input Flit from a neighbor to a corresponding CommuteBuffer.   
     
     
         18 . The method of  claim 12 , wherein the pool of memory resource units are single ported memories with time division access. 
     
     
         19 . The method of  claim 12 , wherein the pool of memory resource units are enabled for synchronous access using a global clock. 
     
     
         20 . A method for debugging a stateful, transaction-oriented runtime system having a multi-level array of storage elements, comprising method operations of:
 instructing the stateful transaction oriented system to pause;   instructing the stateful transaction oriented system to single step until a given point;   tracking information for selected FlowGate invocations; and   querying contents of a portion within the multi-level array of storage elements.   
     
     
         21 . The method of  claim 20 , wherein the method operation of instructing the stateful transaction oriented system to pause includes,
 transmitting a signal to a host system indicating that the system has paused; and   controlling the debugging process through the host system by sending further instructions encapsulated in signals.   
     
     
         22 . The method of  claim 20 , wherein the method operation of tracking information for selected FlowGate invocations includes,
 tracing of firings of FlowGates, including FlowGate input signals, and FlowGate output signals.   
     
     
         23 . The method of  claim 20 , wherein the method operation of querying contents of the portion within the multi-level array of storage elements includes,
 communicating information to a host system, the information including current position of context pointers, contents of a portion of the multi-level array of storage elements or utilization of VirtualChannels.   
     
     
         24 . The method of  claim 20 , further comprising;
 sending executable FlowGate code from a host to the runtime system of a given tile;   loading the FlowGate code into the multi-level storage array; and   executing the FlowGate code.