Capacitor and method for fabricationg the same, and semiconductor device and method for fabricating the same

Abstract

The semiconductor device comprises a device isolation region 14 formed in a semiconductor substrate 10 , a lower electrode 16 formed in a device region 12 defined by the device isolation region and formed of an impurity diffused layer, a dielectric film 18 of a thermal oxide film formed on the lower electrode, an upper electrode 20 formed on the dielectric film, an insulation layer 26 formed on the semiconductor substrate, covering the upper electrode, a first conductor plug 30 a buried in a first contact hole 28 a formed down to the lower electrode, and a second conductor plug 30 b buried in a second contact hole 28 b formed down to the upper electrode, the upper electrode being not formed in the device isolation region. The upper electrode 20 is not formed in the device isolation region 14 , whereby the short-circuit between the upper electrode 20 and the lower electrode 16 in the cavity can be prevented. Thus, a capacitor of high reliability can be provided.

1 . A semiconductor device comprising:
 a device isolation region formed in a semiconductor substrate;   a transistor including a gate insulation film formed of a thermal oxide film formed in a first device region defined by the device isolation region, and a gate electrode formed over the gate insulation film and the device isolation region;   a capacitor including a lower electrode formed in a second device region defined by the device isolation region, a dielectric film formed over the lower electrode and formed of a thermal oxide film thicker than the gate insulation film; and an upper electrode formed over the dielectric film;   an insulation film formed over the semiconductor substrate, covering the transistor and the capacitor;   a first conductor plug buried in a first contact hole which is down to the lower electrode;   a second conductor plug buried in a second contact hole which is down to the upper electrode; and   a third conductor plug buried in a third contact hole which is down to the gate electrode,   the upper electrode of the capacitor being not formed over the device isolation region.   
     
     
         2 . A semiconductor device according to  claim 1 , wherein
 a cavity is formed in the device isolation region near the second device region.   
     
     
         3 . A semiconductor device according to  claim 1 , wherein
 the device isolation region is buried in a trench formed in the semiconductor substrate.   
     
     
         4 . A semiconductor device according to  claim 1 , wherein
 a peak value of a impurity concentration in the lower electrode is 1×10 20  cm −3  or more.   
     
     
         5 . A semiconductor device according to  claim 1 , further comprising
 an etching stopper film formed below the insulation layer and having etching characteristics different from those of the insulation layer.   
     
     
         6 . A semiconductor device according to  claim 1 , wherein the semiconductor substrate is a silicon substrate, and the upper electrode is formed of polysilicon. 
     
     
         7 . A method for fabricating a capacitor comprising the steps of:
 forming a device isolation region in a semiconductor substrate;   forming a sacrifice oxidation film on the surface of the device region defined by the device isolation region;   implanting an impurity in a region containing the device region to form a lower electrode of an impurity diffused layer:   etching off the sacrifice oxidation film;   forming a dielectric film on the surface of the impurity diffused layer by thermal oxidation;   forming an upper electrode over the dielectric film;   forming an insulation layer, covering the upper electrode;   etching the insulation layer to form a first contact hole down to the lower electrode and a second contact hole down to the upper electrode; and   burying the first conductor plug in the first contact hole and burying the second conductor plug in the second contact hole,   in the step of forming the upper electrode, the upper electrode is not formed over the device isolation region.   
     
     
         8 . A method for fabricating a capacitor according to  claim 7 , wherein
 the step of forming the device isolation region includes the step of forming a trench in the semiconductor substrate, the step of forming another insulation layer in the trench and over the semiconductor substrate, and the step of polishing said another insulation layer except in the trench to form the device isolation region of said another insulation layer.   
     
     
         9 . A method for fabricating a capacitor according to  claim 7 , wherein
 in the step of forming the lower electrode, the impurity is implanted with a peak value thereof being 1×10 20  cm −3  or more.   
     
     
         10 . A method for fabricating a capacitor according to  claim 7 ,
 which further comprises, after the step of forming the upper electrode and before the step of forming the insulation layer, the step of forming an etching stopper film having etching characteristics different from those of the insulation layer, covering the upper electrode, and   in which the step of forming the first contact hole and the second contact hole includes the step of etching the insulation layer at a high selectivity ratio to the etching stopper film to form the first contact hole and the second contact hole down to the etching stopper film, and the step of etching off the etching stopper film exposed in the first contact hole and the second contact hole to form the first contact hole down to the upper electrode and the second contact hole down to the lower electrode.   
     
     
         11 . A method for fabricating a semiconductor device comprising the steps of:
 forming a device isolation region in a semiconductor substrate;   forming a sacrifice oxidation film on the surface of a device region defined by the device isolation region and the surface of another device region defined by the device isolation region;   implanting an impurity into a region containing said another device region to form a lower electrode of a impurity diffused layer;   etching off the sacrifice oxidation film;   forming a gate insulation film on the surface of the device region, and a dielectric film thicker than the gate insulation film on the surface of the impurity diffused layer, by thermal oxidation;   forming a gate electrode over the gate insulation film and the device isolation region, and an upper electrode over the dielectric film;   forming an insulation layer, covering the gate electrode and the upper electrode;   etching the insulation layer to form a first contact hole down to the lower electrode, a second contact hole down to the first electrode and a third contact hole down to the gate electrode; and   burying a first conductor plug, a second conductor plug and a third conductor plug respectively in the first contact hole, the second contact hole and the third contact hole,   in the step of forming the upper electrode, the upper electrode being not formed over the device isolation region.   
     
     
         12 . A method for fabricating a capacitor according to  claim 11 , wherein
 the step of forming the device isolation region includes the step of forming a trench in the semiconductor substrate, the step of forming another insulation layer in the trench and over the semiconductor substrate, and the step of polishing said another insulation layer except in the trench to form the device isolation region of said another insulation layer.   
     
     
         13 . A method for fabricating a capacitor according to  claim 11 , wherein
 in the step of forming the lower electrode, the impurity is implanted with a peak value thereof being 1×10 20  cm −3  or more.   
     
     
         14 . A method for fabricating a capacitor according to  claim 11 ,
 which further comprises, after the step of forming the gate electrode and the upper electrode, and before the step of forming the insulation layer, the step of forming an etching stopper film having etching characteristics different from those of the insulation layer, covering the gate electrode and the upper electrode, and   in which the step of forming the first contact hole, the second contact hole and the third contact hole includes the step of etching the insulation layer at a high selectivity ratio to the etching stopper film to form the first contact hole, the second contact hole and the third contact hole down to the etching stopper film, and the step of etching off the etching stopper film exposed in the first contact hole, second contact hole and the third contact hole to form the first contact hole down to the upper electrode, the second contact hole down to the lower electrode and the third contact hole down to the gate electrode.