Display Processing Line Buffers Incorporating Pipeline Overlap

Abstract

Apparatus, systems and methods for display processing line buffers incorporating pipeline overlap are disclosed. For example, an apparatus is disclosed including processing logic to use pixel processing algorithms to process a pixel value of a first portion of an image, and line buffers coupled to the processing logic. The line buffers to hold at least some pixel values of other portions of the image adjacent to the first portion. Where the pixel values of the other portions of the image held by the line buffers correspond to pixel values of the adjacent portions of the image that are to be convolved by the pixel processing algorithms with the pixel value of the first portion. Other implementations are also disclosed.

1 . A method comprising:
 dividing an image to be processed into a plurality of adjacent vertical strips; and   providing line buffers sized based on the size of said vertical strips rather than the size of said image.   
     
     
         2 . The method of  claim 1  including sizing said line buffers to be slightly larger than the size of the strips in order to accommodate pixels adjacent the strip that need to be accommodated. 
     
     
         3 . The method of  claim 1  including determining a pipeline overlap factor for said strips. 
     
     
         4 . An apparatus comprising:
 processing logic to divide an image to be processed into a plurality of adjacent vertical strips; and   line buffers sized based on the size of said vertical strips rather than the size of said image.   
     
     
         5 . The apparatus of  claim 4 , said line buffers sized to be slightly larger than the size of the strips in order to accommodate pixels adjacent the strip that need to be accommodated. 
     
     
         6 . The apparatus of  claim 4 , said processing logic to determine a pipeline overlap factor for said strips. 
     
     
         7 . A system comprising:
 processing logic to use pixel processing algorithms to process a pixel value of a first portion of an image;   memory coupled to the processing logic, the memory to store at least the pixel value of the first portion; and   line buffers coupled to the processing logic, the line buffers to hold at least some pixel values of other portions of the image adjacent to the first portion, wherein the pixel values of the other portions of the image held by the line buffers correspond to pixel values of the adjacent portions of the image that are to be convolved by the pixel processing algorithms with the pixel value of the first portion.   
     
     
         8 . The system of  claim 7 , wherein the memory comprises one of dynamic random access memory (DRAM), static random access memory (SRAM), or non-volatile memory. 
     
     
         9 . The system of  claim 7 , further comprising an antenna to receive the pixel value of the first portion. 
     
     
         10 . The system of  claim 9 , wherein the antenna comprises one of a dipole antenna, a narrowband Meander Line Antenna (MLA), a wideband MLA, an inverted “F” antenna, a planar inverted “F” antenna, a Goubau antenna, or a Patch antenna.