US2011040891A1PendingUtilityA1

System and Method for TCP Offload

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Assignee: ELZUR URIPriority: Aug 30, 2002Filed: Oct 28, 2010Published: Feb 17, 2011
Est. expiryAug 30, 2022(expired)· nominal 20-yr term from priority
Inventors:Uri ElzurFrankie FanSteven B. LindsayScott Mcdaniel
H04L 49/90H04L 47/193H04L 69/161H04L 47/2441H04L 49/9094H04L 47/34H04L 49/9063H04L 69/162H04L 49/9073H04L 69/166H04L 69/16H04L 69/12H04L 69/163H04L 69/10
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Claims

Abstract

A system for processing packets is disclosed and may including a network interface card (NIC). The NIC may include a TCP enabled Ethernet controller (TEEC). The TEEC may include an internal elastic buffer. The TEEC may process received incoming TCP packets once and may temporarily buffer at least a portion of the incoming TCP packets in the internal elastic buffer. The processing may occur without reassembly or retransmission. The internal elastic buffer may include a receive internal elastic buffer and a transmit internal elastic buffer. The receive internal elastic buffer may temporarily buffer at least a portion of the received incoming TCP packets. The transmit internal elastic buffer may temporarily buffer at least a portion of TCP packets to be transmitted. The TEEC may place at least a portion of the received incoming TCP packets data into at least a portion of a host memory.

Claims

exact text as granted — not AI-modified
1 - 33 . (canceled) 
     
     
         34 . A system for processing packets during communication, the system comprising:
 one or more circuits comprising a TCP enabled Ethernet controller (TEEC) and an internal elastic buffer within said TEEC, wherein said one or more circuits receives incoming TCP packets by said TEEC; and   said one or more circuits temporarily buffers at least a portion of said received incoming TCP packets in an internal elastic buffer and processes said at least a portion of said buffered received incoming TCP packet once by said TEEC without reassembly and/or retransmission by said TEEC.   
     
     
         35 . The system according to  claim 34 , wherein said internal elastic buffer comprises a receive internal elastic buffer and a transmit internal elastic buffer. 
     
     
         36 . The system according to  claim 35 , wherein said one or more circuits enables temporary buffering of said at least a portion of said received incoming TCP packets in said receive internal elastic buffer. 
     
     
         37 . The system according to  claim 35 , wherein said one or more circuits enables temporary buffering of at least a portion of TCP packets to be transmitted, in said transmit internal elastic buffer. 
     
     
         38 . The system according to  claim 34 , wherein said one or more circuits places at least a portion of said processed at least a portion of said buffered incoming TCP packets in host memory. 
     
     
         39 . The system according to  claim 34 , wherein said one or more circuits copies at least a portion of said processed at least a portion of said buffered incoming TCP packets to host memory via a single copy operation. 
     
     
         40 . The system according to  claim 34 , wherein said one or more circuits places at least a portion of said processed at least a portion of said buffered incoming TCP packets in a highest hierarchy of buffer available in a host memory. 
     
     
         41 . The system according to  claim 34 , wherein said one or more circuits enables DMA transfer of at least a portion of said processed at least a portion of said buffered incoming TCP packets to a host memory. 
     
     
         42 . The system according to  claim 34 , wherein packets temporarily buffered in said internal elastic buffer are not buffered to enable reassembly by said TEEC. 
     
     
         43 . The system according to  claim 34 , wherein packets temporarily buffered in said internal elastic buffer are not buffered to enable retransmission by said TEEC. 
     
     
         44 . The system according to  claim 34 , wherein said one or more circuits places at least a portion of said processed at least a portion of said buffered incoming TCP packets at least a portion of said processed incoming TCP packet in host buffers in a host memory for processing. 
     
     
         45 . The system according to  claim 34 , wherein said one or more circuits are integrated within a single chip. 
     
     
         46 . The system according to  claim 34 , wherein said one or more circuits are integrated within network interface card (NIC). 
     
     
         47 . A system for processing packets, the system comprising:
 a network interface card (NIC), said NIC comprising;   a TCP enabled Ethernet controller (TEEC), said TEEC comprising,
 an internal elastic buffer, wherein said TEEC processes received incoming TCP packets once and temporarily buffers at least a portion of said incoming TCP packets in said internal elastic buffer, wherein said processing occurs without reassembly or retransmission. 
   
     
     
         48 . The system according to  claim 47 , wherein said internal elastic buffer comprises a receive internal elastic buffer and a transmit internal elastic buffer. 
     
     
         49 . The system according to  claim 48 , wherein said receive internal elastic buffer temporarily buffers at least a portion of said received incoming TCP packets. 
     
     
         50 . The system according to  claim 48 , wherein said transmit internal elastic buffer temporarily buffers at least a portion of TCP packets to be transmitted. 
     
     
         51 . The system according to  claim 47 , wherein said TEEC places at least a portion of said received incoming TCP packets data into at least a portion of a host memory. 
     
     
         52 . The system according to  claim 47 , wherein said NIC utilizes only said internal elastic buffer to temporarily buffer said at least a portion of said received incoming TCP packets. 
     
     
         53 . The system according to  claim 47 , wherein out-of-order TCP packets within said received incoming TCP packets are not stored, re-ordered and/or re-assembled by said TEEC. 
     
     
         54 . The system according to  claim 47 , wherein said NIC does not require a dedicated memory for re-ordering out-of-sequence TCP packets within said received incoming TCP packets. 
     
     
         55 . The system according to  claim 47 , wherein said NIC does not require a dedicated memory for assembling and/or re-ordering IP packets fragmented at an IP layer. 
     
     
         56 . The system according to  claim 47 , wherein said TEEC is enabled to place at least data from said received incoming TCP packets into a highest hierarchy of buffer available in a host memory. 
     
     
         57 . The system according to  claim 47 , wherein said TEEC is enabled to copy at least data from said received incoming TCP packets to a buffer in host memory via a single copy operation. 
     
     
         58 . The system according to  claim 47 , wherein said TEEC is enabled to DMA transfer at least a portion of said processed incoming TCP packets to a host memory. 
     
     
         59 . The system according to  claim 47 , wherein said NIC does not require a TCP offload engine (TOE) dedicated memory for packet retransmission. 
     
     
         60 . The system according to  claim 47 , wherein said NIC does not require a TCP offload engine (TOE) dedicated memory for packet reassembly. 
     
     
         61 . The system according to  claim 47 , wherein said TEEC places at least a portion of said processed received incoming TCP packets into host buffers in a host memory for reassembly. 
     
     
         62 . The system according to  claim 47 , wherein said TEEC comprises a single chip, having integrated therein, said internal elastic buffer. 
     
     
         63 . The system according to  claim 47 , wherein said NIC comprises a single chip, having integrated therein, said TEEC and said internal elastic buffer. 
     
     
         64 . The system according to  claim 47 , wherein said TEEC comprises a single chip, having integrated therein, said internal elastic buffer, and no internal buffers and interfaces to external buffers that are utilized for packet retransmission, packet reassembly and/or packet re-ordering. 
     
     
         65 . A method for processing packets, the method comprising:
 in a TCP enabled Ethernet controller (TEEC), temporarily buffering at least a portion of received incoming TCP packets in an elastic buffer internal to said TEEC, wherein said TEEC is integrated within a network interface card I (NIC); and   processing said temporarily buffered received incoming TCP packets once without reassembly and/or retransmission.   
     
     
         66 . The method according to  claim 65 , wherein said internal elastic buffer comprises a receive internal elastic buffer and a transmit internal elastic buffer. 
     
     
         67 . The method according to  claim 66 , wherein said receive internal elastic buffer temporarily buffers at least a portion of said received incoming TCP packets. 
     
     
         68 . The method according to  claim 66 , wherein said transmit internal elastic buffer temporarily buffers at least a portion of TCP packets to be transmitted. 
     
     
         69 . The method according to  claim 65 , comprising placing by said TEEC, at least a portion of said received incoming TCP packets data into at least a portion of a host memory. 
     
     
         70 . The method according to  claim 65 , wherein said NIC utilizes only said internal elastic buffer to temporarily buffer said at least a portion of said received incoming TCP packets. 
     
     
         71 . The method according to  claim 65 , wherein out-of-order TCP packets within said received incoming TCP packets are not stored, re-ordered and/or re-assembled by said TEEC. 
     
     
         72 . The method according to  claim 65 , wherein said NIC does not require a dedicated memory for re-ordering out-of-sequence TCP packets within said received incoming TCP packets. 
     
     
         73 . The method according to  claim 65 , wherein said NIC does not require a dedicated memory for assembling and/or re-ordering IP packets fragmented at an IP layer. 
     
     
         74 . The method according to  claim 65 , comprising placing by said TEEC, at least data from said received incoming TCP packets into a highest hierarchy of buffer available in a host memory. 
     
     
         75 . The method according to  claim 65 , comprising copying by said TEEC, at least data from said received incoming TCP packets to a buffer in host memory via a single copy operation. 
     
     
         76 . The method according to  claim 65 , comprising DMA transferring by said TEEC, at least a portion of said processed incoming TCP packets to a host memory. 
     
     
         77 . The method according to  claim 65 , wherein said NIC does not require a TCP offload engine (TOE) dedicated memory for packet retransmission. 
     
     
         78 . The method according to  claim 65 , wherein said NIC does not require a TCP offload engine (TOE) dedicated memory for packet reassembly. 
     
     
         79 . The method according to  claim 65 , comprising placing by said TEEC, at least a portion of said processed received incoming TCP packets into host buffers in a host memory for reassembly. 
     
     
         80 . The method according to  claim 65 , wherein said TEEC comprises a single chip, having integrated therein, said internal elastic buffer. 
     
     
         81 . The method according to  claim 65 , wherein said NIC comprises a single chip, having integrated therein, said TEEC and said internal elastic buffer. 
     
     
         82 . The method according to  claim 65 , wherein said TEEC comprises a single chip, having integrated therein, said internal elastic buffer, and no internal buffers and interfaces to external buffers that are utilized for packet retransmission, packet reassembly and/or packet re-ordering.

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