Methods of fabricating memory devices

Abstract

Methods of fabricating a memory device can include forming a plurality of wordlines on a semiconductor substrate. A ground select line can be formed on a first side of the wordlines. A string select line can be formed on a second side of the wordlines. The wordlines can extend between the ground select line and the string select line. First spacers may be formed between the wordlines, between the ground select line and an adjacent one of the wordlines and between the string select line and an adjacent one of the wordlines. Second spacers can be formed on sidewalls of the ground select line and the string select line displaced from the first spacers. The second spacers can be formed from a different material than the first spacers.

What is claimed is: 
     
         1 . A method of fabricating a memory device, comprising:
 forming a plurality of wordlines on a semiconductor substrate;   forming a ground select line on a first side of the wordlines;   forming a string select line on a second side of the wordlines, wherein the wordlines extend between the ground select line and the string select line;   forming first spacers between the wordlines, between the ground select line and an adjacent one of the wordlines and between the string select line and an adjacent one of the wordlines; and   forming second spacers on sidewalls of the ground select line and the string select line displaced from the first spacers, wherein the second spacers are formed from a different material than the first spacers.   
     
     
         2 . The method of  claim 1 , wherein the memory device comprises a nonvolatile memory device and wherein forming a ground select line comprises forming a pair of ground select lines and wherein forming a string select line comprises forming a pair of string select lines and wherein forming the second spacers comprises forming the second spacers on facing sidewalls between the ground select lines and the string select lines, respectively. 
     
     
         3 . The method of  claim 1 , wherein forming the word lines includes an etching process and wherein forming the first spacers is preceded by performing a re-oxidation process on the wordlines following the etching process. 
     
     
         4 . The method of  claim 1 , wherein forming the second spacers comprises:
 forming a silicon nitride layer between the ground select lines and between the string select lines; and   anisotropically etching the silicon nitride layer.   
     
     
         5 . The method of  claim 4 , wherein forming the second spacers is preceded by:
 forming a re-oxidized layer on the ground select lines and the string select lines using a re-oxidation process; and   forming a pad oxide layer on the re-oxidized layer.   
     
     
         6 . The method of  claim 4 , further comprising:
 forming a common source line contacting the second spacers between the ground select lines; and   forming a bitline contact contacting the second spacers between the string select lines.   
     
     
         7 . The method of  claim 6 , wherein the ground select lines and the string select lines each include a hard mask pattern in a top layer thereof and wherein forming the common source line and the bitline contact comprises forming the common source line and the bitline contact self-aligned between the hard mask patterns. 
     
     
         8 . The method of  claim 1 , wherein forming the wordlines comprises:
 forming a gate layer on the semiconductor substrate;   forming hard mask patterns on the gate layer to define regions for the wordlines, the ground select lines and the string select lines;   forming a photoresist pattern to expose the region for the wordlines; and   forming gate patterns using an etching process on the gate layer.   
     
     
         9 . The method of  claim 8 , wherein forming the wordlines is followed by performing a re-oxidation process on the wordlines. 
     
     
         10 . The method of  claim 8 , wherein forming the ground select lines and forming the string select lines comprises:
 forming a photoresist pattern that exposes the regions for the ground select lines and the string select lines and not the region for the wordlines; and then   performing an etching process on the gate patterns.   
     
     
         11 . The method of  claim 10 , wherein forming the second spacers comprises:
 forming a silicon nitride layer between the ground select lines and between the string select lines; and   anisotropically etching the silicon nitride layer.   
     
     
         12 . The method of  claim 11 , wherein forming the second spacers is preceded by:
 forming a re-oxidized layer using a re-oxidation process on the ground select lines and the string select lines; and   forming a pad oxide layer on the re-oxidized layer.   
     
     
         13 . The method of  claim 12 , further comprising:
 forming a common source line contacting the second spacers between the ground select lines; and   forming a bitline contact contacting the second spacers between the string select lines.   
     
     
         14 . The method of  claim 13 , wherein forming the common source line comprises forming the common source line self-aligned between the hard mask patterns in a top layer of the ground select lines and wherein forming the bitline contact comprises forming the bitline contact self-aligned between the hard mask patterns in a top layer of the string select lines. 
     
     
         15 . The method of  claim 8 , wherein forming the gate layer comprises:
 forming a tunnel insulating layer on the semiconductor substrate;   forming a charge storing layer on the tunnel insulating layer;   forming an interlayer insulating layer on the charge storing layer; and   forming a gate conductive layer on the interlayer insulating layer.