Carbon nanotube field emission device with overhanging gate

Abstract

A carbon nanotube field emission device with overhanging gate fabricated by a double silicon-on-insulator process. Other embodiments are described and claimed.

1 . A field emission device comprising:
 a wafer having a hole and comprising a silicon substrate; a first insulator layer on the silicon substrate; a first silicon layer on the first insulator layer; a second insulator layer on the first silicon layer; and a second silicon layer on the second insulator layer, where the hole has a bottom at the silicon substrate; and   at least one carbon nanotube formed at the bottom of the hole.   
     
     
         2 . The field emission device as set forth in  claim 1 , wherein the first and second insulator layers comprise silicon dioxide. 
     
     
         3 . The field emission device as set forth in  claim 1 , wherein the second silicon layer forms a gate with respect to the at least one carbon nanotube. 
     
     
         4 . The field emission device as set forth in  claim 1 , the hole having a top and a sidewall, the second silicon layer forming at least a portion of the sidewall, wherein the second silicon layer at the top of the hole overhangs the sidewall. 
     
     
         5 . A semiconductor process applied to a wafer, the wafer comprising a silicon substrate; a first insulator layer on the silicon substrate; a first silicon layer on the first insulator layer; a second insulator layer on the first silicon layer; and a second silicon layer on the second insulator layer; the semiconductor process comprising:
 etching through the second silicon layer, through the second insulator layer, and through the first silicon layer to the first insulator layer to define a hole;   lateral etching in the first silicon layer to laterally enlarge the hole at the first silicon layer;   etching through the first insulator layer to the substrate, so that the hole has a bottom that includes the substrate; and   forming an array of carbon nanotubes at the bottom of the hole on the substrate.   
     
     
         6 . The semiconductor process as set forth in  claim 5 , where forming the array of carbon nanotubes at the bottom of the hole on the substrate comprises:
 depositing photoresist material on the substrate at the bottom of the hole.   
     
     
         7 . A semiconductor process as set forth in  claim 6 , where forming the array of carbon nanotubes at the bottom of the hole on the substrate further comprises:
 patterning the photoresist material to provide a pattern for a catalyst;   depositing the catalyst on the substrate at the bottom of the hole; and   growing the array of carbon nanotubes on the catalyst.   
     
     
         8 . The semiconductor process as set forth in  claim 5 , where forming the array of carbon nanotubes at the bottom of the hole on the substrate comprises:
 depositing photoresist material on the wafer so that the photoresist material bridges the opening of the hole.   
     
     
         9 . The semiconductor process as set forth in  claim 8 , where forming the array of carbon nanotubes at the bottom of the hole on the substrate further comprises:
 patterning the photoresist material to provide a pattern for a catalyst;   depositing the catalyst on the substrate at the bottom of the hole; and   growing the array of carbon nanotubes on the catalyst.