US2011058340A1PendingUtilityA1

Method of forming a multilayer substrate core structure using sequential microvia laser drilling and substrate core structure formed according to the method

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Assignee: LI YONGGANGPriority: Jun 28, 2007Filed: Nov 8, 2010Published: Mar 10, 2011
Est. expiryJun 28, 2027(~1 yrs left)· nominal 20-yr term from priority
H05K 3/422H05K 3/4602Y10T29/49165H05K 3/0035H05K 3/4652H05K 3/40H05K 2201/0394H05K 2201/09563Y10T29/49128B23K 26/382
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Claims

Abstract

A method of fabricating a substrate core structure, and a substrate core structure formed according to the method. The method includes: laser drilling a first set of via openings through a starting insulating layer; filling the first set of via openings with a conductive material to provide a first set of conductive vias; providing first and second patterned conductive layers on opposite sides of the starting insulating layer; providing a supplemental insulating layer onto the first patterned conductive layer; laser drilling a second set of via openings through the supplemental insulating layer; filling the second set of via openings with a conductive material to provide a second set of conductive vias; and providing a supplemental patterned conductive layer onto an exposed side of the supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer and the supplemental patterned conductive layer at opposite sides thereof.

Claims

exact text as granted — not AI-modified
1 . An assembly comprising:
 a package substrate, the package substrate including
 a starting insulating layer having a first side and an opposing second side, the starting insulating layer including a number of vias extending from the first side to the second side, each of the vias in the starting insulating layer including a conical shape and filled with a material including copper; 
 a first patterned conductive layer disposed on the first side of the starting insulating layer, the first patterned conductive layer comprised of a material including copper, at least one of the vias in the starting insulating layer contacting the first patterned conductive layer; 
 a second patterned conductive layer disposed on the second side of the starting insulating layer, the second patterned conductive layer comprised of a material including copper, at least one of the vias in the starting insulating layer contacting the second patterned conductive layer; 
 a first insulating layer disposed on the first patterned conductive layer and exposed portions of the first side of the starting insulating layer, the first insulating layer including a first set of vias, each via of the first set having a conical shape and filled with a material including copper; 
 a third patterned conductive layer disposed on the first insulating layer, the third patterned conductive layer comprised of a material including copper, wherein at least one via of the first set contacts the first and third patterned conductive layers; 
 a second insulating layer disposed on the second patterned conductive layer and exposed portions of the second side of the starting insulating layer, the second insulating layer including a second set of vias, each via of the second set having a conical shape and filled with a material including copper; and 
 a fourth patterned conductive layer disposed on the second insulating layer, the fourth patterned conductive layer comprised of a material including copper, wherein at least one via of the second set contacts the second and fourth patterned conductive layers; and 
   an integrated circuit (IC) device coupled with the package substrate.   
     
     
         2 . The assembly of  claim 1 , wherein at least one via in the starting insulating layer, at least one via of the first set, and at least one via of the second set are aligned. 
     
     
         3 . The assembly of  claim 1 , wherein at least one of the vias in the starting insulating layer includes a diameter in a range between about 50 and 300 microns. 
     
     
         4 . The assembly of  claim 1 , wherein a pitch of the vias in the starting insulating layer is in a range of about 150 microns or greater. 
     
     
         5 . The assembly of  claim 1 , wherein the IC device includes a processing system. 
     
     
         6 . The assembly of  claim 5 , further comprising a memory device coupled with the package substrate. 
     
     
         7 . The assembly of  claim 1 , wherein the conical shape included in each via in the starting insulating layer is formed by laser drilling. 
     
     
         8 . The assembly of  claim 7 , wherein the vias in the starting insulating layer are formed from a first direction.

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