Semiconductor memory device having local sense amplifier with on/off control

Abstract

A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.

1 . A semiconductor memory device comprising:
 a plurality of memory cells;   a pair of local input/output lines comprising a local input/output line and an inverted local input/output line coupled to one or more of the memory cells;   a pair of global input/output lines comprising a global input/output line and an inverted global input/output line;   a local sense amplifier amplifying voltages of data signals output from the local input/output lines and transmitting the data to the global input/output lines in response to a local sense control signal; and   a data sense amplifier amplifying voltages of data signals output from the data input/output lines connected to the global input/output lines and outputting the data from the semiconductor memory device in response to a sensing enable signal,   wherein the data sense amplifier is a current type sense amplifier.   
     
     
         2 . The semiconductor memory device of  claim 1 , further comprising:
 a load transistor unit allowing current to flow through the global input/output lines in response to a load signal; and   a selection switching unit connecting the data sense amplifier to one of the memory cell array blocks in response to a selection signal,   wherein the load transistor unit comprises:   a first load transistor having a first terminal to which a first voltage is applied, a second terminal connected to the global input/output line, and a gate to which the load signal is input; and   a second load transistor having a first terminal to which the first voltage is applied, a second terminal connected to the inverted global input/output line, and a gate to which the load signal is input.   
     
     
         3 . The semiconductor memory device of  claim 1 , further comprising a local input/output line pre charge controller for pre charging voltages of the local input/output lines to a predetermined voltage in response to precharge control signals. 
     
     
         4 . A semiconductor memory device comprising:
 a plurality of memory cells;   a bit line sense amplifier amplifying voltages of data output from a pair of bit lines connected to the memory cells and transmitting the data to a pair of local input/output lines;   a local sense amplifier amplifying voltages of data output from the local input/output lines and transmitting the data to a pair of global input/output lines in response to a local sense control signal;   a data sense amplifier amplifying voltages of data output from a pair of data input/output lines connected to the global input/output lines and outputting the data from the semiconductor memory device in response to a sensing enable signal; and   a controller activating the local sense control signal for a predetermined duration in response to a first signal and a second signal.   
     
     
         5 . The semiconductor memory device of  claim 4 , wherein the first signal is activated in response to a row active command, and the local sense amplifier is activated for a predetermined duration after the first signal is activated. 
     
     
         6 . The semiconductor memory device of  claim 4 , wherein the first signal is a bit line sense enable signal which activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. 
     
     
         7 . The semiconductor memory device of  claim 4 , wherein the second signal is activated or deactivated to be in phase with a column selection line signal that connects the bit lines and the local input/output lines. 
     
     
         8 . The semiconductor memory device of  claim 4 , wherein the controller comprises:
 a pulse generator generating a first pulse signal activated for a predetermined duration in response to the first signal; and   a local sense control signal generator activating the local sense control signal when both the first pulse signal and the second signal are activated, and deactivating the local sense control signal when the second signal is deactivated.   
     
     
         9 . The semiconductor memory device of  claim 8 , wherein the pulse generator comprises:
 a first delayer delaying the first signal;   a first inverter inverting an output of the first delayer; and   a first AND gate unit performing an AND operation on an output of the first inverter and the first signal to generate the first pulse signal.   
     
     
         10 . The semiconductor memory device of  claim 8 , wherein the local sense control signal generator comprises:
 a first transmission gate transmitting or blocking the first pulse signal in response to the second signal;   a latch unit latching an output of the first transmission gate;   a second transmission gate transmitting or blocking an output of the latch unit in response to the second signal;   a second inverter inverting an output of the second transmission gate; and   a second AND gate unit performing an AND operation on an output of the second inverter and the second signal to generate the local sense control signal.   
     
     
         11 . The semiconductor memory device of  claim 4 , further comprising a local input/output line precharge controller for precharging the local input/output lines in response to a precharge control signal,
 wherein the controller further comprises a pre charge control signal generator activating the precharge control signal for a predetermined duration when the local sense control signal is deactivated.   
     
     
         12 . The semiconductor memory device of  claim 11 , wherein the precharge control signal generator comprises:
 a third inverter inverting the local sense control signal;   a second delayer delaying an output of the third inverter;   a fourth inverter inverting an output of the second delayer; and   a third AND gate unit performing an AND operation on the output of the third inverter and an output of the fourth inverter to generate the precharge control signal.   
     
     
         13 . The semiconductor memory device of  claim 4 , wherein the controller is located in a periphery region outside a memory core. 
     
     
         14 . The semiconductor memory device of  claim 4 , wherein the data sense amplifier is one of a current type sense amplifier and a voltage type sense amplifier. 
     
     
         15 . A semiconductor memory device comprising:
 a plurality of memory cells;   a bit line sense amplifier amplifying voltages of data output from a pair of bit lines connected to the memory cells and transmitting the data to a pair of local input/output lines;   a local sense amplifier amplifying voltages of data output from the local input/output lines and transmitting the data to a pair of global input/output lines in response to a predetermined signal;   a data sense amplifier amplifying voltages of data output from a pair of data input/output lines connected to the global input/output lines and outputting the data from the semiconductor memory device in response to a sensing enable signal; and   a local sense amplifier controller generating the predetermined signal which controls the local sense amplifier in response to a control signal and a local sense control signal,   wherein the local sense amplifier operates in response to the local sense control signal when the control signal is activated, and does not operate when the control signal is deactivated.   
     
     
         16 . The semiconductor memory device of  claim 15 , wherein the local sense amplifier controller performs an AND operation on the control signal and the local sense control signal to generate the predetermined signal. 
     
     
         17 . The semiconductor memory device of  claim 15 , wherein the control signal is activated or deactivated by one of a mode register set and a fuse unit. 
     
     
         18 . The semiconductor memory device of  claim 15 , wherein the data sense amplifier is one of a current type sense amplifier and a voltage type sense amplifier. 
     
     
         19 - 40 . (canceled)