Solid state memory wear concentration

Abstract

A memory system includes a volatile memory and a non-volatile memory. The volatile memory is configured as a random access memory or cache for the nonvolatile memory. Wear concentration logic targets one or more selected devices of the nonvolatile memory for accelerated wear.

1 . A memory system comprising:
 a volatile memory;   a non-volatile memory;   the volatile memory configured as one or both of a cache and a random access memory for the nonvolatile memory; and   wear concentration logic to target one or more selected devices of the nonvolatile memory for accelerated wear.   
     
     
         2 . The memory system of  claim 1 , further comprising:
 the volatile memory is DRAM and the nonvolatile memory is NAND flash.   
     
     
         3 . The memory system of  claim 1 , further comprising:
 logic to determine when the selected devices are nearing or at end of useful life; and   logic to provide an indication to an operator that the selected devices require replacement.   
     
     
         4 . The memory system of  claim 1 , further comprising:
 logic to isolate the selected devices from system power and signals automatically when they are nearing or at end of useful life.   
     
     
         5 . The memory system of  claim 1 , further comprising:
 a slice controller comprising logic to map addresses of the nonvolatile memory to addresses of the selected devices.   
     
     
         6 . The memory system of  claim 1 , further comprising:
 logic to copy data from the selected devices when the selected devices are full or nearly full of data; and   logic to erase the selected devices after copying the data.   
     
     
         7 . The memory system of  claim 1 , further comprising:
 logic to track write frequency of memory locations of the nonvolatile memory.   
     
     
         8 . A method comprising:
 operating, a volatile memory and a nonvolatile flash memory; and   mapping write-backs from the volatile memory to the flash memory to cause selected devices of the flash memory to experience accelerated wear.   
     
     
         9 . The method of  claim 8 , further comprising:
 the volatile memory is DRAM and the nonvolatile memory is NAND flash.   
     
     
         10 . The method of  claim 8 , further comprising:
 determining when the selected devices are nearing or at end of useful life; and   providing an indication to a human operator that the selected devices require replacement.   
     
     
         11 . The method of  claim 8 , further comprising:
 isolating the selected devices from system power and signals automatically when they are nearing or at end of useful life.   
     
     
         12 . The method of  claim 8 , further comprising:
 copying data from the selected devices to other devices of the nonvolatile memory when the selected devices are full or nearly full of data; and   erasing the selected devices after copying the data.   
     
     
         13 . The method of  claim 8 , further comprising:
 tracking a write frequency of memory locations of the nonvolatile memory.   
     
     
         14 . The method of  claim 8 , further comprising:
 mapping addresses of the nonvolatile memory to addresses of the selected, devices in a slice controller.   
     
     
         15 . A device comprising:
 a host processor;   a volatile memory configured to service memory reads and writes for the host processor;   a non-volatile main memory; and   wear concentration logic to target one or more selected devices of the nonvolatile memory for accelerated wear by preferentially redirecting write-backs from the volatile memory to the selected, devices.   
     
     
         16 . The device of  claim 15 , further comprising:
 the volatile memory is DRAM and the nonvolatile memory is NAND flash.   
     
     
         17 . The device of  claim 15 , further comprising:
 logic to determine when the selected devices are nearing or at end of useful life; and   logic to provide an indication to an operator of the device that the selected devices require replacement.   
     
     
         18 . The device of  claim 15 , further comprising:
 logic to isolate the selected devices from system power and signals automatically when they are nearing or at end of useful life.   
     
     
         19 . The device of  claim 15 , further comprising:
 a slice controller comprising logic to map addresses of the nonvolatile memory to addresses of the selected devices.   
     
     
         20 . The device of  claim 15 , further comprising:
 logic to copy data from the selected devices when the selected devices are full or nearly full of data; and   logic to erase the selected devices after copying the data.   
     
     
         21 . A memory system comprising:
 wear concentration logic to target one or more selected devices of a nonvolatile memory for accelerated wear.   
     
     
         22 . The memory system of  claim 21 , further comprising:
 logic to determine when the selected devices are nearing or at end of useful life; and   logic to provide an indication to an operator that the selected devices require replacement.   
     
     
         23 . The memory system of  claim 21 , further comprising:
 logic to isolate the selected devices from system power and signals automatically when they are nearing or at end of useful life.   
     
     
         24 . The memory system of  claim 21 , further comprising:
 logic to copy data from the selected devices when the selected devices are full or nearly full of data; and   logic to erase the selected devices after copying the data.   
     
     
         25 . The memory, system of  claim 21 , further comprising:
 logic to track write frequency of memory locations of the nonvolatile memory.