Method of Manufacturing a Fast Recovery Rectifier

Abstract

A fast recovery rectifier structure with the combination of Schottky structure to relieve the minority carriers during the forward bias condition for the further reduction of the reverse recovery time during switching in addition to the lifetime killer such as Pt, Au, and/or irradiation. This fast recovery rectifier uses unpolished substrates and thick impurity diffusion for low cost production. A reduced p-n junction structure with a heavily doped film is provided to terminate and shorten the p-n junction space charge region. This reduced p-n junction with less total charge in the p-n junction to further improve the reverse recovery time. This reduced p-n junction can be used alone, with the traditional lifetime killer method, with the Schottky structure and/or with the epitaxial substrate.

1 . A method of manufacturing a rectifier, comprising:
 forming a first semiconductor layer with a first type of dopant;   depositing a second semiconductor layer of a second type of dopant above said first semiconductor layer, wherein said first type of dopant and said second type of dopant have opposite polarity;   depositing a thin film of a third semiconductor layer of said second type of dopant immediately above said second semiconductor layer, wherein doping concentration of said third semiconductor layer is higher than doping concentration of said second semiconductor layer to create an early termination at the interface of said second semiconductor layer and said third semiconductor layer; and   depositing a metal layer above said third semiconductor layer, wherein the interface between said metal layer and said third semiconductor layer is an ohmic contact.   
     
     
         2 . The method of  claim 1 , further comprising epitaxial forming a fourth semiconductor layer with said first type of dopant between said first semiconductor layer and said second semiconductor layer, wherein doping concentration of said fourth semiconductor layer is lower than doping concentration of said first semiconductor layer. 
     
     
         3 . The method of  claim 1 , wherein said first type of dopant is n-type. 
     
     
         4 . The method of  claim 1 , wherein said first semiconductor layer further comprising one or more lifetime killer materials including Pt or Au. 
     
     
         5 . The method of  claim 1 , wherein depositing a thin film of said third semiconductor layer further comprises performing an implantation. 
     
     
         6 . The method of  claim 5 , wherein performing implantation includes using implant dose from about 1.0e 12  per cm 2  to about 1.0e 15  per cm 2 . 
     
     
         7 . The method of  claim 5 , wherein performing implantation includes using implant energy from about 500 eV to about 50 KeV. 
     
     
         8 . The method of  claim 5 , wherein doping concentration of said second semiconductor layer is approximately 2 to 10 times of said first semiconductor layer. 
     
     
         9 . The method of  claim 1 , wherein depositing a thin film of said third semiconductor layer further comprises performing a diffusion. 
     
     
         10 . The method of  claim 9 , wherein performing diffusion includes using diffusion temperature from about 700° C. to about 1100° C. 
     
     
         11 . The method of  claim 9 , wherein performing diffusion includes diffusion time from about 60 second to about 1 hour. 
     
     
         12 . The method of  claim 9 , wherein junction voltage between said first semiconductor layer and said second semiconductor layer is from about 0.5 eV to about 0.9 eV. 
     
     
         13 . The method of  claim 2 , wherein said second semiconductor layer which is above said forth semiconductor layer is formed by performing implantation with implant dose from about 1.0e 10  per cm 2  to about 1.0e 16  per cm 2  and implant energy from about 100 V to about 100 KeV and time from about 10 seconds to about 1 hour and temperature from about 600° C. to about 1100° C.