Latency based platform coordination

Abstract

In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.

1 . An electronic apparatus, comprising:
 a root complex; and   a bridge to couple one or more components to the root complex;   the root complex to be able to receive from the bridge latency tolerance information from at least one of the one or more components, the bridge to be able to provide to the root complex snoop and non snoop tolerance information from the at least one of the one or more components.   
     
     
         2 . The electronic apparatus of  claim 1 , wherein the root complex when executing comprises a policy engine to determine a latency tolerance value from the received latency tolerance information and to determine a power management policy for the root complex using the latency tolerance value. 
     
     
         3 . The electronic apparatus of  claim 2 , wherein the latency tolerance value is a worst-case tolerance value and the power management policy ensures that the root complex is not idle in excess of the worst-case tolerance value. 
     
     
         4 . The electronic apparatus of  claim 2 , wherein the root complex is at least partially implemented with a CPU chip. 
     
     
         5 . The electronic apparatus of  claim 2 , wherein the bridge is implemented within the CPU chip. 
     
     
         6 . The electronic apparatus of  claim 2 , wherein the policy engine is to compute minimum latency tolerance value 
     
     
         7 . An electronic apparatus, comprising:
 at least one processor; and   a bridge comprising logic to:
 receive latency data from one or more components coupled to the bridge; and 
 provide the latency data to the processor to compute a latency tolerance value from the latency data and determine a power management policy from the latency tolerance value. 
   
     
     
         8 . The electronic apparatus of  claim 7 , wherein the processor is to implement a policy engine to receive a snoop latency tolerance and a non-snoop latency tolerance from the one or more components 
     
     
         9 . The electronic apparatus of  claim 8 , wherein the bridge has at least one delay value for data transmitted via the bridge/switch device and the bridge deducts the delay value from the latency data. 
     
     
         10 . The electronic apparatus of  claim 9 , wherein the bridge comprises a first delay value when the bridge is in a low power state and a second delay value when the bridge is in an active power state, and the bridge deducts one of the first delay value or the second delay value from the latency data. 
     
     
         11 . The electronic apparatus of  claim 7 , wherein the processor is to implement a policy engine to:
 compare a plurality of latency values received from a plurality of components; and   select the lowest latency value from the plurality of latency values.   
     
     
         12 . The electronic apparatus of  claim 7 , wherein the processor is to implement a policy engine to monitor latency values over time during operation of the electronic apparatus and update power management policies as a function of changes in the latency tolerance values. 
     
     
         13 . An apparatus, comprising:
 logic to generate latency tolerance data to be provided to a bridge coupled to the apparatus, the bridge to be part of a computing device comprising a root complex.   
     
     
         14 . The apparatus of  claim 13 , in which the root complex is to enter into a power management state based on the latency tolerance data provided it to it from the apparatus.