Semiconductor circuit including electrostatic discharge circuit having protection element and trigger transistor

Abstract

A semiconductor circuit includes a first pad for a first power source, a second pad for a second power source, a third pad for an input/output signal, a protection element arranged between the first pad and the third pad, and a transistor functioning as a trigger element for use in passing a trigger current through the protection element. The transistor includes source connected to the third pad, a gate and a backgate commonly connected to the second pad.

1 . A semiconductor circuit comprising:
 a first pad for a first power source;   a second pad for a second power source;   a third pad for an input/output signal;   a protection element arranged between the first pad and the third pad; and   a transistor functioning as a trigger element for use in passing a trigger current through the protection element, said transistor including a source connected to the third pad, a gate and a backgate commonly connected to the second pad.   
     
     
         2 . The semiconductor circuit according to  claim 1 ,wherein the protection element comprises a silicon controlled rectifier (SCR), wherein an anode of the SCR is connected to the first pad, wherein a cathode of the SCR is connected to the third pad, andwherein a gate of the SCR is connected to a drain of the transistor. 
     
     
         3 . The semiconductor circuit according to  claim 2 , wherein the SCR comprises: a member of a P-type substrate or a P-well;
 a first P 3+  region formed at the member and connected to the second pad;   a first N +  region formed at the member and connected to the third pad;   an N-well formed at the P-type substrate or adjacent to the P-well;   a second P +  region formed at the N-well and connected to the first pad; and   a second N +  region formed at the N-well and connected to a drain of the transistor.   
     
     
         4 . The semiconductor circuit as claimed in  claim 1 , wherein said transistor comprises a NMOS transistor, said first power source comprises VDD, and said second power source comprises VSS. 
     
     
         5 . The semiconductor circuit as claimed in  claim 1 , wherein said second pad is at a ground level, the first pad is at a power supply voltage level, and said third pad is supplied with a signal always higher than the ground level.