Non-Volatile Memory Devices Having Reduced Susceptibility to Leakage of Stored Charges and Methods of Forming Same

Abstract

Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern.

1 .- 19 . (canceled) 
     
     
         20 . A semiconductor device comprises:
 a substrate:   a tunnel insulating layer over the substrate;   a charge storage pattern over the tunnel insulating layer, the charge storage pattern having an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall;   a blocking layer comprising an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern; and   a gate electrode over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern,   wherein a thickness of a portion of the blocking layer covering the edge portion is greater than a thickness of the other portion of the blocking layer.   
     
     
         21 . The semiconductor device of  claim 20 , wherein the insulating pattern and the gate dielectric layer are provided through different processes. 
     
     
         22 . The semiconductor device of  claim 20 , wherein the insulating pattern and the gate dielectric layer are provided with a discontinuous surface therebetween, and are divided by the discontinuous surface. 
     
     
         23 . The semiconductor device of  claim 20 , wherein the edge portion of the charge storage pattern is a curved surface, the insulating pattern is extended from the edge portion to the upper surface of the charge storage pattern, and a thickness of a portion of the blocking layer covering the upper surface of the charge storage pattern is greater than a thickness of the blocking layer covering the sidewall of the charge storage pattern. 
     
     
         24 . The semiconductor device of  claim 23 , wherein the insulating pattern is extended from the edge portion to a bottom surface of the charge storage pattern along the sidewall of the charge storage pattern. 
     
     
         25 . The semiconductor device of  claim 23 , wherein the gate dielectric layer covers the insulating pattern. 
     
     
         26 . The semiconductor device of  claim 25 , wherein the blocking layer further comprises a spacer including different materials from the gate dielectric layer, the spacer covering the gate dielectric layer and being disposed over the edge portion of the charge storage pattern. 
     
     
         27 . The semiconductor device of  claim 20 , wherein the insulating pattern comprises different materials from the gate dielectric layer, and is disposed over the gate dielectric layer. 
     
     
         28 . The semiconductor device of  claim 27 , wherein an upper surface of the insulating pattern is higher than the upper surface of the charge storage pattern, and a bottom surface of the insulating pattern is higher than a bottom surface of the charge storage pattern and is lower than the upper surface of the charge storage pattern. 
     
     
         29 . The semiconductor device of  claim 27 , wherein the gate electrode comprises a lower gate electrode having an upper surface of the same height as a height of a bottom surface of the insulating pattern and an upper gate electrode disposed over the lower gate electrode, and the lower gate electrode and the upper gate electrode comprises a discontinuous surface between an upper surface of the lower gate electrode and a bottom surface of the upper gate electrode.