Semiconductor device including resistance storage element

Abstract

A phase change memory includes a memory cell with a phase change element storing data according to level change of a resistance value in association with phase change, a write circuit converting the phase change element to an amorphous state or a polycrystalline state according to the logic of write data in a write operation mode, a read circuit reading out stored data from the phase change element in a readout operation mode, and a discharge circuit applying a discharge voltage to the phase change element to remove electrons trapped in the phase change element in a discharge operation mode. Accordingly, variation in the resistance value at the phase change element can be suppressed.

1 - 24 . (canceled) 
     
     
         25 . A semiconductor device comprising:
 a memory cell array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines provided corresponding to said plurality of rows, respectively, and a plurality of bit lines provided corresponding to said plurality of columns, respectively,   each memory cell including a phase change element storing data according to level change of a resistance value in association with phase change, and a transistor having a gate connected to a corresponding word line, and connected to a corresponding bit line in series with said phase change element,   a write circuit applying a write voltage according to a logic of write data to a phase change element of a selected memory cell to set the resistance value of said phase change element in a write operation mode,   a read circuit applying a read voltage to a phase change element of a selected memory cell to read out stored data from said phase change element based on current flowing to said phase change element in a readout operation mode, and   a discharge circuit applying a discharge voltage to one electrode of a phase change element in each memory cell and setting the other electrode at an open state to remove charge trapped at each phase change element in a discharge operation mode.   
     
     
         26 . The semiconductor device according to  claim 25 , wherein
 said transistor has its drain connected to a corresponding bit line via a corresponding phase change element, and receives a ground voltage at its source,   said discharge circuit sets each word line at the ground voltage, and applies a positive voltage to each bit line as said discharge voltage in said discharge operation mode.   
     
     
         27 . The semiconductor device according to  claim 25 , wherein
 said memory array further includes a source line provided common to said plurality of memory cells,   said transistor has its drain connected to a corresponding bit line via a corresponding phase change element, and its source connected to said source line, and   said discharge circuit sets each word line at a positive voltage and each bit line at an open state, and applies a positive voltage to said source line as said discharge voltage in said discharge operation mode.   
     
     
         28 . The semiconductor device according to  claim 25 , wherein
 said memory array further includes a source line and a well line provided common to said plurality of memory cells,   said transistor has its drain connected to a corresponding bit line via a corresponding phase change element, its source connected to said source line, and its substrate connected to said well line, and   said discharge circuit sets each word line at a ground voltage and each bit line at an open state, sets said source line at one of a positive voltage and an open state, and applies a positive voltage to said well line as said discharge voltage.   
     
     
         29 . The semiconductor device according to  claim 25 , wherein
 said memory array further includes a source line provided common to said plurality of memory cells,   said transistor has its drain connected to a corresponding bit line via a corresponding phase change element, and its source connected to said source line, and   said discharge circuit sets each word line at one end of a positive voltage and ground voltage, applies a positive voltage to each bit line as said discharge voltage, and sets said source line at an open state in said discharge operation mode.   
     
     
         30 . The semiconductor device according to  claim 25 , wherein
 said memory array further includes a source line and a well line provided common to said plurality of memory cells,   said transistor has its drain connected to a corresponding bit line via a corresponding phase change element, its source connected to said source line, and its substrate connected to said well line, and   said discharge circuit sets each word line at a negative voltage and each bit line at an open state, applies a negative voltage to said source line as said discharge voltage, and sets said well line at a negative voltage in said discharge operation mode.   
     
     
         31 . The semiconductor device according to  claim 25 , wherein
 said memory array further includes a well line provided common to said plurality of memory cells,   said transistor has its drain connected to a corresponding bit line, receives a ground voltage at its source via a corresponding phase change element, and has its substrate connected to said well line,   said discharge circuit sets each word line at a negative voltage, and applies a negative voltage to each bit line as said discharge voltage, and sets said well line at a negative voltage in said discharge operation mode.   
     
     
         32 . The semiconductor device according to  claim 25 , wherein
 said memory array further includes a source line provided common to said plurality of memory cells,   said transistor has its drain connected to a corresponding bit line, and its source connected to said source line via a corresponding phase change element, and   said discharge circuit sets each word line at a ground voltage, and applies a positive voltage to said source line as said discharge voltage in said discharge operation mode.   
     
     
         33 . The semiconductor device according to  claim 25  wherein
 said memory array further includes a source line and a well line provided common to said plurality of memory cells, 
 said transistor has its drain connected to a corresponding bit line, its source connected to said source line via a corresponding phase change element, and its substrate connected to said well line, and 
 said discharge circuit sets each word line at a ground voltage, each bit line at one of a positive voltage and an open state, said source line at an open state, and applies a positive voltage to said well line as said discharge voltage in said discharge operation mode. 
 
     
     
         34 . The semiconductor device according to  claim 25 , wherein said discharge circuit is rendered active in response to a discharge pulse signal, and
 further comprises a pulse generation circuit generating said discharge pulse signal in response to one of a write activation signal activating said write circuit, a read activation signal activating said read circuit, a chip activation signal activating said semiconductor device, a module activation signal activating a module in said semiconductor device, and a discharge designation signal designating execution of said discharge operation.