Back-light control circuit of multi-lamps liquid crystal display

Abstract

A multi-lamps LCD panel back-light control circuit is provided, and which includes a control unit, a full bridge switch, a resonance network circuit, a voltage transformer, and a feedback network. The control unit operates in coordinating with the full bridge switch, the resonance network circuit, the voltage transformer and the feedback network so as to use a constant operating frequency and a PWM feedback to control a current of CCFLs. The back-light control circuit is characterized in that different integrated-circuits (ICs) are respectively formed from the control unit including a PWM controller, a triangular wave/clock generator, a ½ frequency divider, and a logic circuit. The different ICs have either a plurality of respective frequency synchronous signal control terminals or a plurality of phase synchronous signal control terminals that are connected to one another so that the different ICs operate respectively either with a same operating frequency or a same phase.

1 . A multi-lamps liquid crystal display (LCD) panel back-light control circuit, comprising a control unit, a full bridge switch, a resonance network circuit, a voltage transformer, and a feedback network, wherein the control unit operates in coordinating with the full bridge switch, the resonance network circuit, the voltage transformer and the feedback network so as to use a constant operating frequency and a pulse width modulation (PWM) feedback to control a current of cold cathode fluorescent lamps (CCFLs), the back-light control circuit being characterized in that different integrated circuits (ICs) are respectively formed from the control unit comprising a PWM controller, a triangular wave/clock generator, a ½ frequency divider, and a logic circuit, the different ICs having either a plurality of respective frequency synchronous signal control terminals or a plurality of phase synchronous signal control terminals that are connected to one another so that the different ICs operate respectively either with a same operating frequency or a same phase. 
     
     
         2 . The multi-lamps LCD panel back-light control circuit of  claim 1 , wherein a power switch of the full bridge switch outputs a duty cycle that is controlled and changed via the PWM controller of the control unit, while a ground switch of the full bridge switch outputs a constant duty cycle controllable above 50%;
 wherein a phase relationship between a signal that controls the ground switch and a signal that controls the power switch is constant, the ground switch being formed from at least an NMOSFET and the power switch being formed at least from a PMOSFET; and   wherein with a common drain connection of the ground switch and the power switch, the power switch is turned off when the ground switch is turned on, and without a common drain connection, the power switch is turned on only after a preset delay from a turn on of the ground switch.   
     
     
         3 . The multi-lamps LCD panel back-light control circuit of  claim 2 , wherein the power switch of the full bridge is formed from two PMOSFETs and the ground switch is formed from two NMOSFETs. 
     
     
         4 . The multi-lamps LCD panel back-light control circuit of  claim 2 , wherein the PWM controller includes an error amplifier which has an output with a voltage level that is compared to an outputted triangular wave via a comparator before obtaining a PWM output wave. 
     
     
         5 . The multi-lamps LCD panel back-light control circuit of  claim 2 , wherein the ½ frequency divider transforms the clock of the triangular wave/clock generator to a half frequency clock signal with a frequency equal to a half of the triangular wave, an inverter inverting the half frequency clock signal to an inverted half frequency clock signal; the half clock signal and the inverted half clock signal being outputted through a delay and an OR logic to generate an output signal having a duty cycle greater than 50% and delayed from the half clock signal, wherein the delay time is adjustable by means of a delay time controller element. 
     
     
         6 . The multi-lamps LCD panel back-light control circuit of  claim 2 , wherein a changed duty cycle output generated from the PWM controller is calculated as the result of an AND logic from the half clock signal and the output of the PWM controller, thereby the output of the PWM controller is in an outputting state only when the half clock signal is in a “1” logic state, the delay being adjustable by means of controller elements, and the AND logic enables the output of the PWM controller to be turned on only after a delay from the turn on of the NMOSFET; wherein the PMOSFET being of low driving voltage and the NMOSFET being of high driving voltage, the inverter and the logic transform the PWM output to push the PMOSFET. 
     
     
         7 . The multi-lamps LCD panel back-light control circuit of  claim 2 , wherein the operating frequency and the synchronization of the operating phase of the triangular wave generator and the ½ frequency divider are controlled via a plurality of external synchronous signals delivered through terminals thereof. 
     
     
         8 . The multi-lamps LCD panel back-light control circuit of  claim 1 , wherein a phase of the current of respective CCFLs is in similar configuration within an operation of the CCFLs with a same frequency. 
     
     
         9 . The multi-lamps LCD panel back-light control circuit of  claim 1 , wherein the triangular wave/clock generator comprises:
 a raising edge detector circuit comprising a first inverter and a first NAND gate, wherein an input terminal of the first inverter is coupled to a first input terminal of the first NAND gate, and an output terminal of the first inverter is coupled to a second input terminal of the first NAND gate;   a first comparator having a first input terminal receiving a relative high threshold voltage;   a second comparator having a first input terminal receiving a relative low threshold voltage, a second input terminal coupled to a second input terminal of the first comparator;   an AND gate having a first input terminal coupled to an output terminal of the first comparator, a second input terminal coupled to an output terminal of the first NAND gate;   a second NAND gate having a first input terminal coupled to an output terminal of the AND gate and an output terminal outputting a CLK signal;   a third NAND gate having a first input terminal coupled to an output terminal of the second comparator, a second input terminal coupled to the output terminal of the second NAND gate and an output terminal coupled to a second input terminal of the second NAND gate;   a second inverter having an input terminal coupled to the corresponding frequency synchronous signal control terminal and an output terminal coupled to the input terminal of the first inverter;   a first NMOSFET having a gate coupled to the output terminal of the second NAND gate, a source coupled to a ground and a drain coupled to the input terminal of the second inverter;   a capacitor having a first terminal coupled to the second input terminal of the second comparator and a second terminal coupled to the ground;   a PMOSFET having a gate coupled to the output terminal of the second NAND gate and a drain coupled to the first terminal of the capacitor;   a first current source coupled between a system voltage and a source of the PMOSFET;   a second NMOSFET having a gate coupled to the output terminal of the second NAND gate and a drain coupled to the first terminal of the capacitor; and   a second current source coupled between a source of the second NMOSFET and the ground.   
     
     
         10 . The multi-lamps LCD panel back-light control circuit of  claim 9 , wherein the ½ frequency divider comprising:
 a D flip-flop having a clock terminal receiving the CLK signal and a first output terminal outputting a ½ CLK signal; 
 a third inverter having an input terminal coupled to the corresponding phase synchronous signal control terminal and an output terminal coupled to a data input terminal of the D flip-flop; and 
 a third NMOSFET having a gate coupled to a second output terminal of the D flip-flop, a drain coupled to the input terminal of the third inverter and a source coupled to the ground. 
 
     
     
         11 . The multi-lamps LCD panel back-light control circuit of  claim 1 , further comprising:
 a first pull-up resistor coupled between a system voltage and the frequency synchronous signal control terminals when all of the frequency synchronous signal control terminals are coupled each other; and   a second pull-up resistor coupled between the system voltage and the phase synchronous signal control terminals when all of the phase synchronous signal control terminals are coupled each other.   
     
     
         12 . The multi-lamps LCD panel back-light control circuit of  claim 1 , wherein the resonance network circuit comprises an inductor and a capacitor that are placed in the voltage transformer either in a primary side or a secondary side. 
     
     
         13 . The multi-lamps LCD panel back-light control circuit of  claim 12 , wherein the inductor of the resonance network circuit is either a separate and independent element from the voltage transformer or a leakage inductor generated by the voltage transformer. 
     
     
         14 . The multi-lamps LCD panel back-light control circuit of  claim 12 , wherein a secondary capacitor of the resonance network circuit is either an independent element or a parasitic capacitor generated between CCFLs and the LCD panel.