Semiconductor memory device having advanced tag block

Abstract

A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal.

1 . A semiconductor memory device, comprising:
 a row decoding block configured to decode a row address, and to output a decoded word line address and a logical cell block address for accessing one of N number of cell blocks;   a tag block configured to receive the row address, the logical cell block address, and to convert the logical cell block address into a physical cell block address for accessing one of N+1 number of cell blocks;   an address latching block configured to latch the decoded word line address to output a word line activation signal as a latched word line in response to the physical cell block address;   a cell area configured to output data in response to the word line activation signal; and   a control unit configured to control the tag block, the row decoding block and a predetermined cell block table, which activates one word line of a cell block selected from the plurality of cell blocks by the physical cell block address.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein the cell area includes N+1 number of cell blocks, each including M number of word lines; and the row address accesses data included in N number of cell blocks, each including M number of word lines. 
     
     
         3 . The semiconductor memory device of  claim 2 , wherein the logical cell block address corresponds to N number of cell blocks; and the physical unit cell block address corresponds to N+1 number of cell blocks. 
     
     
         4 . The semiconductor memory device of  claim 3 , wherein the address latching block includes N+1 number of decoded address latches. 
     
     
         5 . The semiconductor memory device of  claim 4 , wherein the decoded address latch corresponding to each of M number of word lines has M number of latch blocks. 
     
     
         6 . The semiconductor memory device of  claim 5 , wherein the latch blocks includes:
 a normal word line latch configured to receive the decoded word line address and to generate the word line activation signal in response to an internal control signal; and   a predetermined word line latch configured to receive the decoded word line address to output the internal control signal in response to a word line selection signal and to generate the word line activation signal in response to the internal control signal and the physical cell block address.   
     
     
         7 . The semiconductor memory device of  claim 4 , wherein the decoded address latch corresponding to each of M number of word lines has P number of main latch blocks, each having Q number of sub latch blocks, wherein M=P×Q. 
     
     
         8 . An operation method of a semiconductor memory device, comprising:
 decoding a row address and outputting a decoded word line address and a logical cell block address for accessing one of N number of cell blocks;   activating a physical cell block address for accessing one of N+1 number of cell blocks based on a tag memory in response to a decoded row address;   selecting a latch in response to the decoded row address activating a select word line based on a selected latch in an activated physical cell block; and   accessing data corresponding to an activated word line.   
     
     
         9 . The operation method of a semiconductor memory device of  claim 8 , wherein the activating of the physical cell block includes converting the logical cell block address into the physical cell block address. 
     
     
         10 . The operation method of a semiconductor memory device of  claim 9 , wherein the selecting of the latch includes latching the decoded word line address to output a word line activation signal as a latched word line in response to the physical cell block address. 
     
     
         11 . The operation method of a semiconductor memory device of  claim 10 , wherein the selecting of the latch includes outputting an internal control signal in response to a word line selection signal and generating the word line activation signal in response to the internal control signal and the physical cell block address. 
     
     
         12 . The operation method of a semiconductor memory device of  claim 10 , wherein the accessing of data corresponding to an activated word line includes outputting data in response to the word line activation signal. 
     
     
         13 . The operation method of a semiconductor memory device of  claim 8 , wherein each of N+1 number of cell blocks includes M number of word lines and the row address accesses data included in N number of cell blocks, each including M number of word lines. 
     
     
         14 . The operation method of a semiconductor memory device of  claim 8 , wherein the logical cell block address corresponds to N number of cell blocks and the physical unit cell block address corresponds to N+1 number of cell blocks.