Semiconductor Device

Abstract

This application relates to a semiconductor device comprising a first chip comprising a first electrode on a first face of the first chip, and a second chip attached to the first electrode, wherein the second chip comprises a transformer comprising a first winding and a second winding.

1 . A semiconductor device comprising:
 a first chip comprising a first electrode on a first face of the first chip; and   a second chip attached to the first electrode, the second chip comprising a transformer comprising a first winding and a second winding, wherein a backside of the second chip is in direct contact with the first electrode on the first face of the first chip.   
     
     
         2 . The semiconductor device according to  claim 1  wherein the second chip is attached to the first electrode by means of at least one of soldering, diffusion soldering, sintering, an electrically conducting glue, and anodic bonding. 
     
     
         3 . The semiconductor device according to  claim 1  wherein the surface area of the first electrode of the first chip is larger than the area of the backside of the second chip. 
     
     
         4 . The semiconductor device according to  claim 1  wherein the first chip comprises a second electrode on a second face opposite to the first face of the first chip. 
     
     
         5 . The semiconductor device according to  claim 4  wherein the first chip comprises at least one third electrode and wherein the second winding is electrically coupled to the at least one third electrode of the first chip. 
     
     
         6 . The semiconductor device according to  claim 4  wherein the second winding is electrically coupled to the at least one third electrode of the first chip by means of at least one of a bond wire, a bond ribbon and an electrically conducting structured film. 
     
     
         7 . The semiconductor device according to  claim 4  wherein the second chip comprises an integrated circuit electrically coupled with the second winding and with the at least one third electrode of the first chip. 
     
     
         8 . The semiconductor device according to  claim 1  further comprising a carrier comprising a first island to which the first chip is attached. 
     
     
         9 . The semiconductor device according to  claim 1  wherein the first winding and the second winding are coplanar to each other. 
     
     
         10 . The semiconductor device according to  claim 9  wherein the distance between the plane of the first winding and the plane of the second winding is smaller than 100 micrometer. 
     
     
         11 . The semiconductor device according to  claim 1  wherein the first chip comprises a power transistor. 
     
     
         12 . The semiconductor device according to  claim 11  wherein the first electrode of the first chip is a source contact or a emitter contact of the power transistor, and wherein the second electrode of the first chip is a drain contact or a collector contact of the power transistor. 
     
     
         12 . A semiconductor chip comprising:
 a first electrode on a first face of the semiconductor chip;   a second electrode on a second face of the semiconductor chip opposite to the first face;   a transformer comprising a first winding and a second winding; and   at least one third electrode on the first face of the semiconductor chip, the third electrode is electrically coupled to the second winding.   
     
     
         13 . The semiconductor chip according to  claim 12  wherein at least one third electrode is coupled to the second winding by a bond wire. 
     
     
         14 . The semiconductor chip according to  claim 12  comprising a dielectric layer applied to the plane of the second winding, and wherein the first winding is applied to the dielectric layer. 
     
     
         15 . A semiconductor device comprising:
 a first chip comprising a first power transistor having a first source contact or a first emitter contact, a first drain contact or a first collector contact, and a first gate contact or a first base contact;   a second chip rigidly attached to the first source contact or the first emitter contact, the second chip comprising a transformer to control the first gate contact or the first base contact, wherein a backside of the second chip is in direct contact with the first source contact of the first power transistor; and   a third chip comprising a second power transistor having a second source contact or a second emitter contact, a second drain contact or a second collector contact, the second drain contact or the second collector contact being electrically connected with the first source contact or the first emitter contact, and a second gate contact or a second base contact.   
     
     
         16 . The semiconductor device according to  claim 15  further comprising a fourth chip rigidly attached to the second source contact or the second emitter contact, the fourth chip comprising a further transformer to control the second gate contact or the second base contact. 
     
     
         17 . The semiconductor device of  claim 1 , wherein the first winding and the second winding are separated from one another by a dielectric layer. 
     
     
         18 . The semiconductor device of  claim 1 , wherein the second chip comprises an integrated circuit electrically connected to the second winding by a first line extending to a first end of the second winding and a second line extending to a second end of the second winding. 
     
     
         19 . The semiconductor device of  claim 12 , wherein the second chip comprises an integrated circuit electrically connected to the second winding by a first line extending to a first end of the second winding and a second line extending to a second end of the second winding. 
     
     
         20 . The semiconductor device of  claim 16 , wherein the second chip and the fourth chip each comprising an integrated circuit configured to receive input from the further transfer signal and convert the input signals to voltages on the second gate contact or the second base contact.