Write signal generator with delay calibration

Abstract

An aligned write signal generator with alignment calibration utilizes an alignment unit to align a plurality of write signal. The aligned write signal generator includes a write signal generator for receiving an EFM signal and converting the EFM signal into a plurality of write signals according to a write strategy waveform generating rule, an alignment unit for receiving the plurality of write signals, aligning the write signals and outputting phase adjusted write signals, and a phase calibration unit for receiving the phase adjusted write signals, detecting phase error between the phase adjusted write signals, and outputting phase control signals. The alignment unit further receives the phase control signals to adjust the delay time of each write signal.

1 . An aligned write signal generator with alignment calibration, comprising:
 a write signal generator for receiving an EFM signal and converting the EFM signal into a plurality of write signals according to a write strategy waveform generating rule;   a first alignment unit for receiving the write signals, delaying at least one of the write signals according to a plurality of phase control signals and outputting a plurality of phase adjusted write signals, wherein the first alignment unit generates a plurality of preset phase adjusted write signals at a calibration mode; and   a phase calibration unit for receiving the preset phase adjusted write signals, and detecting the phase errors among the preset phase adjusted write signals at the calibration mode to adjust the phase control signals, wherein the phase calibration unit outputs the adjusted phase control signals at a normal mode, wherein the phase calibration unit comprises:   a phase detector for receiving the phase adjusted write signals and outputting a phase error signal;   a charge pump for receiving the phase error signal and generating a control current according to the phase error signal;   an integrator for receiving the control current, integrating the control current, and then generating an error voltage; and   a delay time control unit for outputting the phase control signals according to the error voltage;   a multiplexer module having a plurality of multiplexers, each of which has a first input terminal and a second input terminal, wherein the first input terminals of the multiplexers receive a calibration clock, the second input terminals of the multiplexers receive the phase adjusted write signal, respectively, and the multiplexer module outputs the calibration clock when a control signal is enabled and outputs the phase adjusted write signal when the control signal is disabled; and   a second alignment unit comprising a plurality of delay units for respectively receiving the signals outputted from the multiplexer module and outputting signals to the phase detector.   
     
     
         2 . The aligned write signal generator according to  claim 1 , wherein the switch outputs the up-counting signal and the down-counting signal to the delay units of the second alignment unit of the phase calibration unit when the control signal is enabled and outputs the up-counting signal and the down-counting signal to the delay units of the first alignment unit when the control signal is disabled. 
     
     
         3 . An aligned write signal generator with alignment calibration, comprising:
 a write signal generator for receiving an EFM signal and converting the EFM signal into a plurality of write signals according to a write strategy waveform generating rule;   a first alignment unit for receiving the write signals, delaying at least one of the write signals according to a plurality of phase control signals and outputting a plurality of phase adjusted write signals, wherein the first alignment unit generates a plurality of preset phase adjusted write signals at a calibration mode; and   a phase calibration unit for receiving the preset phase adjusted write signals, and detecting the phase errors among the preset phase adjusted write signals at the calibration mode to adjust the phase control signals, wherein the phase calibration unit outputs the adjusted phase control signals at a normal mode, wherein the phase calibration unit comprises:   a phase detector for receiving the phase adjusted write signals and outputting a phase error signal;   a charge pump for receiving the phase error signal and generating a control current according to the phase error signal;   an integrator for receiving the control current, integrating the control current, and then generating an error voltage; and   a delay time control unit for outputting the phase control signals according to the error voltage;   a selection switch for receiving the phase adjusted write signals and selecting two of the phase adjusted write signal to be outputted to the phase detector,   wherein the delay time control unit comprises:   a first comparator for comparing the error voltage with a first reference voltage and outputting a first comparison signal, wherein the first comparison signal is of high level when the error voltage is higher than the first reference voltage;   a second comparator for comparing the error voltage with a second reference voltage and outputting a second comparison signal, wherein the second comparison signal is of high level when the error voltage is less than the second reference voltage;   a first AND gate for receiving the first comparison signal and a trigger clock, and generating an up-counting signal;   a second AND gate for receiving the second comparison signal and the trigger clock, and generating a down-counting signal; and   a switch for receiving the up-counting signal and the down-counting signal, and outputting the up-counting signal and the down-counting signal as the phase control signals to one of the delay units according to a switch signal;   wherein the first reference voltage is higher than or equal to the second reference voltage,   wherein the phase calibration unit further comprises:   a multiplexer module having a plurality of multiplexers, each of which has a first input terminal and a second input terminal, wherein the first input terminals of the multiplexers receive a calibration clock, the second input terminals of the multiplexers receive the phase adjusted write signal, respectively, and the multiplexer module outputs the calibration clock when a control signal is enabled and outputs the phase adjusted write signal when a control signal is disabled; and   a second alignment unit comprising a plurality of delay units for respectively receiving the signals outputted from the multiplexers of the multiplexer module and outputting signals to the phase detector.   
     
     
         4 . The aligned write signal generator according to  claim 3 , wherein the switch outputs the up-counting signal and the down-counting signal to the delay units of the second alignment unit of the phase calibration unit when the control signal is enabled and outputs the up-counting signal and the down-counting signal to the delay units of the first alignment unit when the control signal is disabled.