Integrated circuit package having a castellated heatspreader

Abstract

In one aspect, an embodiment of an IC package includes an IC chip electrically connected to a substrate, a heatspreader disposed over the IC chip, wherein the heatspreader does not directly contact the IC chip, and an encapsulant material encapsulating at least a portion of the IC chip and a portion of the heatspreader such that a top portion of the heatspreader is exposed to the surroundings of the IC package. In another embodiment, the heatspreader comprises at least one castellation to improve adhesion to the encapsulation compound. A method of manufacturing such IC package is also disclosed.

1 . A method for fabricating an integrated circuit package, comprising the steps of:
 a) etching a leadframe strip to define a leadframe having a first surface and an opposing second surface;   b) attaching a semiconductor die having a first surface and an opposing second surface to said leadframe by mounting said first surface of said semiconductor die on said first surface of said leadframe;   c) fixing said leadframe strip and a heat sink strip to a mold, said heat sink strip having a first surface facing said semiconductor die and an opposing second surface, wherein said heat sink strip is disposed in close proximity to said semiconductor die and a cavity exists between said heat sink strip and said leadframe strip when fixed to said mold;   d) encapsulating said cavity with an encapsulation compound, wherein said first surface of said leadframe strip, said second surface of said semiconductor die, and said first surface of said heat sink strip are embedded in said encapsulation compound, such that a layer of encapsulation compound separates said heat sink strip from said semiconductor die and said leadframe strip;   e) singulating said integrated circuit package from said leadframe, said heat sink strip and said encapsulation compound.   
     
     
         2 . The method according to  claim 1 , further comprising the step of etching said first surface of said heat sink strip to define at least one castellation extending from said first surface of said heat sink strip. 
     
     
         3 . The method according to  claim 2 , wherein said etching step produces an undercut in at least one surface of said castellation. 
     
     
         4 . The method according to  claim 1 , further comprising the step of attaching at least one castellation on said first surface of said heat sink strip. 
     
     
         5 . The method according to  claim 1 , further comprising the step of etching said first surface of said heat sink strip to define a central castellation extending from said first surface of said heat sink strip, a center of said central castellation aligned to a center of said semiconductor die. 
     
     
         6 . The method according to  claim 5 , wherein said etching step produces an undercut in at least one surface of said central castellation. 
     
     
         7 . The method according to  claim 1 , further comprising the step of attaching a central castellation on said first surface of said heat sink strip. 
     
     
         8 . The method according to  claim 1 , further comprising attaching a metal clip to at least one side of said integrated circuit package, said metal clip contacts said second surface of said heat sink strip and a surface of said integrated circuit package opposing said second surface of said heat sink strip.