Clock data recovery and synchronization in interconnected devices

Abstract

For synchronizing a master device and a slave device connected by a data transfer link, the master device measures a phase offset in a signal received from the slave device with respect to the master's clock signal. The master determines a control symbol based on the phase offset. The master encodes the control symbol in a transmit signal for the slave. The slave decodes the control symbol from the signal received from the master. The slave uses the control symbol to adjust the phase shift to compensate for the phase offset of a signal to be transmitted to the master device. When the phase compensated signal is received at the master, its phase offset is smaller than the original phase offset. This procedure can be performed iteratively until the phase offset is within a desired tolerance.

1 . In a system having at least two interconnected devices, wherein a first device and a second device are connected by a data transfer link, the first device including a clock source and the second device including a phase lock loop, a method for reducing a phase offset of a signal received at the first device, comprising:
 at the first device,   transmitting a prior signal from the first device to the second device in accordance with a clock signal from the clock source;   at the second device,   receiving the prior signal at the second device to form a received prior signal;   applying the phase lock loop to the received prior signal to form a recovered clock signal synchronized to the received prior signal;   generating a first transmit signal in accordance with the recovered clock signal;   transmitting the first transmit signal to the first device;   at the first device,   receiving the first transmit signal to form a first received signal;   measuring the phase offset between the first received signal and the clock signal to form a first phase offset; and   adjusting the first received signal to reduce the first phase offset to form a phase compensated received signal.   
     
     
         2 . The method of  claim 1 , wherein at the first device, the step of measuring the phase offset further comprises:
 comparing a signal phase of the first received signal to a clock phase of the clock signal to determine the first phase offset.   
     
     
         3 . The method of  claim 1 , wherein the first received signal contains a training pattern represented at the first device in a reference training pattern, the step of measuring the phase offset further comprising:
 at the first device,   extracting the training pattern from the first received signal to form a received training pattern; and   comparing the received training pattern with the reference training pattern to determine the first phase offset.   
     
     
         4 . The method of  claim 1 , further comprising:
 at the first device,   inserting a training pattern in the prior signal for the step of transmitting a prior signal, wherein at the second device, the received prior signal contains the training pattern, wherein the step of generating a first transmit signal includes inserting the training pattern in the first transmit signal.   
     
     
         5 . The method of  claim 1 , wherein at the first device, the step of adjusting the first received signal further comprises:
 adjusting a clock phase of the clock signal to reduce the first phase offset forming a phase compensated clock signal; and   forming the phase compensated received signal in accordance with the phase compensated clock signal.   
     
     
         6 . The method of  claim 1 , wherein the second device includes an analog to digital converter, the method further comprising:
 at the second device,   sampling an analog signal using the analog to digital converter to form a plurality of signal samples; and   encoding the signal samples to form the first transmit signal.   
     
     
         7 . The method of  claim 1 , wherein the first device comprises a field programmable gate array performing the steps of the first device. 
     
     
         8 . The method of  claim 1 , wherein the second device comprises a field programmable gate array performing the steps of the second device. 
     
     
         9 . In a system having at least two interconnected devices, wherein a first device and a second device are connected by a data transfer link, an apparatus for reducing a phase offset of a signal received at the first device, comprising:
 at the first device,   a clock source that generates a clock signal;   a first transmitter coupled to the data transfer link and the clock source, the first transmitter forming a prior signal in accordance with the clock signal and transmitting the prior signal over the data transfer link to the second device;   at the second device,   a second receiver coupled to the data transfer link, the second receiver receiving the prior signal to form a received prior signal;   a phase lock loop coupled to receive the received prior signal, the phase lock loop generating a recovered clock signal synchronized with the received prior signal;   a second transmitter responding to the recovered clock signal to form a first transmit signal synchronized with the recovered clock signal, the second transmitter transmitting the first transmit signal over the data transfer link to the first device;   at the first device,   a first receiver that receives the first transmit signal to form a first received signal;   a phase comparator coupled to the first receiver and the clock source, the phase comparator measuring the phase offset between the first received signal and the clock signal to form a first phase offset; and   a phase compensator coupled to receive the first received signal, the first phase offset and the clock signal, the phase compensator adjusting the first received signal to reduce the first phase offset to form a phase compensated received signal.   
     
     
         10 . The apparatus of  claim 9 , wherein at the first device, the phase comparator compares a signal phase of the first received signal to a clock phase of the clock signal to determine the first phase offset. 
     
     
         11 . The apparatus of  claim 9 , wherein the first received signal contains a training pattern represented at the first device in a reference training pattern, the phase comparator further comprising:
 a pattern decoder coupled to the first receiver and extracting the training pattern from the first received signal to form a received training pattern; and   a data comparator coupled to the pattern decoder and comparing the received training pattern to the reference training pattern to determine the first phase offset.   
     
     
         12 . The apparatus of  claim 9 , further comprising:
 at the first device,   a training pattern generator coupled to the first transmitter and inserting a training pattern in the prior signal, the first transmitter transmitting the prior signal over the data transfer link; and   at the second device,   a loopback controller coupled to the second receiver and the second transmitter, the second receiver receiving the prior signal to form a received prior signal containing the training pattern and the second transmitter responding to the loopback controller to transmit the training pattern in a second prior signal over the data transfer link to the first device, the second prior transmit signal forming the first received signal at the first device.   
     
     
         13 . The apparatus of  claim 9 , wherein the phase compensator further comprises:
 a clock phase adjuster coupled to receive the clock signal and the first phase offset, the clock phase adjuster applying a phase shift to the clock signal to reduce the first phase offset forming a phase compensated clock signal, wherein the phase compensator responds to the phase compensated clock signal to form the phase compensated received signal.   
     
     
         14 . The apparatus of  claim 9 , wherein the second device further comprises:
 an analog to digital converter coupled to receive an analog signal and producing a plurality of signal samples; and   a signal encoder coupled to receive the signal samples from the analog to digital converter, the signal encoder encoding the signal samples to form the first transmit signal.   
     
     
         15 . The apparatus of  claim 9 , wherein the first device is implemented in a field programmable gate array. 
     
     
         16 . The apparatus of  claim 9 , wherein the second device is implemented in a field programmable gate array. 
     
     
         17 . In a system having a master device connected to a plurality of slave devices by a plurality of data transfer links, wherein each of a plurality of signals received at the master device has a corresponding phase offset, an apparatus for reducing each phase offset, comprising:
 at the master device,   a clock source that generates a clock signal;   a plurality of first transmitters, each first transmitter coupled to a corresponding data transfer link and the clock source, each first transmitter forming a corresponding prior signal in accordance with the clock signal and transmitting the corresponding prior signal to a corresponding slave device;   at each slave device,   a second receiver coupled to the corresponding data transfer link, the second receiver receiving the corresponding prior signal to form a received prior signal;   a phase lock loop coupled to receive the received prior signal, the phase lock loop generating a recovered clock signal synchronized with the received prior signal;   a second transmitter responding to the recovered clock signal to form a corresponding first transmit signal synchronized with the recovered clock signal, the second transmitter transmitting the corresponding first transmit signal over the corresponding data transfer link to the master device;   at the master device,   a plurality of first receivers, each first receiver receiving the corresponding first transmit signal to form a corresponding first received signal;   a plurality of phase comparators, each phase comparator coupled to a corresponding first receiver and the clock source, each phase comparator measuring the phase offset between the corresponding first received signal and the clock signal to form a corresponding first phase offset; and   a plurality of phase compensators, each phase compensator coupled to receive the corresponding first received signal and the corresponding first phase offset, each phase compensator adjusting the corresponding first received signal to reduce the corresponding first phase offset to form a corresponding phase compensated received signal.