Interconnection structures for semicondcutor devices

Abstract

An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.

1 . An interconnection structure for a semiconductor device, comprising:
 an inter-level insulation layer disposed on a semiconductor substrate;   first contact constructions penetrating the inter-level insulation layer;   second contact constructions penetrating the inter-level insulation layer; and   metal interconnections connecting the first contact constructions to the second contact constructions on the inter-level insulation layer;   wherein the first contact constructions comprise first and second plugs stacked in sequence and the second contact constructions comprise the second plug.   
     
     
         2 . The interconnection structure as set forth in  claim 1 , wherein a minimum pitch of the metal interconnections is less than about 0.1 μm. 
     
     
         3 . The interconnection structure as set forth in  claim 1 , further comprising:
 gate layers interposed between the inter-level insulation layer and the semiconductor substrate, the gate layers being connected to the metal interconnections by the second contact constructions.   
     
     
         4 . The interconnection structure as set forth in  claim 1 , wherein the first plug comprises polycrystalline silicon;
 wherein the second plug comprises a first barrier metal layer and a first metal layer, the first barrier metal layer comprising titanium, titanium-nitride, tungsten-nitride, tantalum, and/or tantalum-nitride, the first metal layer comprising tungsten, aluminum, and/or copper; and   wherein the metal interconnections comprise a second barrier metal layer and a second metal layer, the second barrier metal layer comprising titanium, titanium-nitride, tungsten-nitride, tantalum, and/or tantalum-nitride, the second metal layer comprising tungsten, aluminum, and/or copper.   
     
     
         5 . The interconnection structure as set forth in  claim 1 , wherein the semiconductor substrate comprises a cell array region where cell transistors are arranged with cell impurity regions and cell gate layers, a low voltage region where low voltage transistors are arranged with low voltage impurity regions and low voltage gate layers, and a high voltage region where high voltage transistors are arranged with high voltage impurity regions and high voltage gate layers; and
 wherein the cell impurity regions are partially connected to the metal interconnections by the first contact constructions, and the cell gate layers, the low voltage gate layers, and the high voltage gate layers are connected to the metal interconnections by the second contact constructions.   
     
     
         6 . The interconnection structure as set forth in  claim 5 , wherein the low voltage impurity regions are connected to the metal interconnections by the first contact constructions and the high voltage impurity regions are connected to the metal interconnections by the second contact constructions. 
     
     
         7 . The interconnection structure as set forth in  claim 5 , wherein the high voltage impurity regions are connected to the metal interconnections by the first contact constructions and the low voltage impurity regions are connected to the metal interconnections by the second contact constructions. 
     
     
         8 . The interconnection structure as set forth in  claim 5 , wherein the high voltage and low voltage impurity regions are connected to the metal interconnections by the first contact constructions. 
     
     
         9 . The interconnection structure as set forth in  claim 5 , wherein the high voltage and low voltage impurity regions are connected to the metal interconnections by the second contact constructions. 
     
     
         10 . The interconnection structure as set forth in  claim 5 , wherein the cell gate layers comprise a floating gate electrode layer, a gate inter-level insulation layer, and a control gate layer, and the cell transistors and the metal interconnections form a cell array architecture of a NAND flash memory. 
     
     
         11 . The interconnection structure as set forth in  claim 1 , wherein the inter-level insulation layer has a top surface, wherein the first contact constructions penetrate the inter-level insulation layer while exposing the top surface of the inter-level insulation layer, wherein the second contact constructions penetrate the inter-level insulation layer while exposing the top surface of the inter-level insulation layer, and wherein the metal interconnections are disposed directly on the top surface of the inter-level insulation layer. 
     
     
         12 . An interconnection structure for a semiconductor device, comprising:
 a semiconductor substrate comprising a cell array region, a low voltage region, and a high voltage region;   cell transistors disposed in the cell array region, which comprises cell impurity regions and cell gate layers;   low voltage transistors disposed in the low voltage region, which comprises low voltage impurity regions and low voltage gate layers;   high voltage transistors disposed in the high voltage region, which comprises high voltage impurity regions and high voltage gate layers;   metal interconnections disposed on the semiconductor substrate;   first contact constructions connecting the cell impurity regions to the metal interconnections; and   second contact constructions connecting the metal interconnections to the cell gate layers, the low voltage gate layers, and the high voltage gate layers;   wherein the first contact constructions comprise first and second plugs stacked in sequence and the second contact constructions comprise the second plugs.   
     
     
         13 . The interconnection structure as set forth in  claim 12 , wherein the first plug comprises polycrystalline silicon;
 wherein the second plug comprises a first barrier metal layer and a first metal layer, the first barrier metal layer comprising titanium, titanium-nitride, tungsten-nitride, tantalum, and/or tantalum-nitride, the first metal layer comprising tungsten, aluminum, and/or copper; and   wherein the metal interconnection comprises a second barrier metal layer and a second metal layer, the second barrier metal layer comprising titanium, titanium-nitride, tungsten-nitride, tantalum, and/or tantalum-nitride, the second metal layer comprising tungsten, aluminum, and/or copper.   
     
     
         14 . The interconnection structure as set forth in  claim 12 , wherein the low voltage impurity regions are connected to the metal interconnections by one of the first and second contact constructions and the high voltage impurity regions are connected to the metal interconnections by the other one of the first and second contact constructions. 
     
     
         15 . The interconnection structure as set forth in  claim 12 , wherein the cell transistors and the metal interconnections comprise a cell array architecture of a NAND flash memory. 
     
     
         16 . The interconnection structure as set forth in  claim 12 , wherein a minimum pitch of the metal interconnections is less than about 0.1 μm.