Chip-type electric double layer capacitor cell and method of manufacturing the same

Abstract

There is provided a chip-type electric double layer capacitor comprising: a resin case having a housing space provided therein and formed of insulating resin and first and second external terminals inserted into the resin case by insert injection molding. Each of the external terminals has a first portion exposed to an outer surface of the resin case for external contact and a second portion exposed to an inner surface of the housing space for internal contact. a sealing portion includes a groove portion provided in the resin case along a circumference of at least one of the first and second external terminals and a resin filling the groove portion. An electric double layer capacitor cell is mounted in the housing space and electrically connected to the second portion of the first and second external terminals.

1 . A chip-type electric double layer capacitor comprising:
 a lower case having a housing space of which a top surface is opened and a first joint element provided along an upper end of a sidewall enclosing the housing space;   an upper cap mounted on the lower case so as to cover the housing space, and having a second joint element provided at an edge adjacent area corresponding to the first joint element and conforming to a shape of the first joint element;   first and second external terminals inserted into the lower case by insert injection molding, each having a first portion exposed to an outer surface of the lower case for external contact and a second portion exposed to an inner surface of the housing space for internal contact; and   an electric double layer capacitor cell mounted in the housing space and electrically connected to the second portion of the first and second external terminals,   wherein the first and second joint elements have a welded portion therebetween such that the housing space of the lower case is sealed by the upper cap, and   the upper cap includes a shielding portion provided inwardly of the second joint element and extending downwardly.   
     
     
         2 . The chip-type electric double layer capacitor of  claim 1 , wherein the shielding portion extends downwardly so as to be lower than the welded portion. 
     
     
         3 . The chip-type electric double layer capacitor of  claim 2 , wherein the shielding portion is spaced apart from the second joint element. 
     
     
         4 . The chip-type electric double layer capacitor of  claim 1 , wherein the shielding portion is pressed and attached to an upper surface of the electric double layer capacitor cell mounted in the housing space. 
     
     
         5 . The chip-type electric double layer capacitor of  claim 1 , wherein the first joint element is a recess stepped towards the housing space and the second joint element is a projection corresponding to the recess. 
     
     
         6 . The chip-type electric double layer capacitor of  claim 5 , wherein the welded portion is obtained such that a welding portion prepared at an end of the projection is welded on a surface thereof in contact with the recess. 
     
     
         7 . The chip-type electric double layer capacitor of  claim 1 , wherein the first portion of the first and second external terminals is exposed to the same outer surface of the lower case, and
 the same outer surface is provided as a mounting surface for the chip-type electric double layer capacitor.   
     
     
         8 . The chip-type electric double layer capacitor of  claim 7 , wherein the second portion of the first and second external terminals extends to side surfaces connected to the mounting surface. 
     
     
         9 . The chip-type electric double layer capacitor of  claim 1 , wherein the electric double layer capacitor cell is electrically connected to the second portion of the first and second external terminals by welding or ultrasonic welding. 
     
     
         10 . A method of manufacturing a chip-type electric double layer capacitor, the method comprising:
 preparing a lower case having a housing space of which a top surface is opened, a first joint element formed along an upper end of a sidewall enclosing the housing space, and first and second external terminals inserted therein by insert injection molding in order that each of the first and second external terminals has a first portion exposed to an outer surface of the lower case and a second portion exposed to an inner surface of the housing space;   mounting an electric double layer capacitor cell in the housing space and electrically connecting the electric double layer capacitor cell to the second portion of the first and second external terminals exposed to the inner surface of the housing space;   mounting an upper cap on the lower case, the upper cap having a second joint element formed at an edge adjacent area corresponding to the first joint element and conforming to a shape of the first joint element; and   welding the first and second joint elements to have a welded portion therebetween such that the housing space of the lower case is sealed by the upper cap,   wherein the upper cap further includes a shielding portion formed inwardly of the second joint element and extending downwardly.   
     
     
         11 . The method of  claim 10 , wherein the shielding portion extends downwardly so as to be lower than the welded portion. 
     
     
         12 . The method of  claim 11 , wherein the shielding portion is spaced apart from the second joint element. 
     
     
         13 . The method of  claim 10 , wherein the welding of the first and second joint elements is performed while allowing the shielding portion to be pressed and attached to an upper surface of the electric double layer capacitor cell mounted in the housing space. 
     
     
         14 . The method of  claim 10 , wherein the first joint element is a recess stepped towards the housing space and the second joint element is a projection corresponding to the recess. 
     
     
         15 . The method of  claim 14 , wherein, in the welding of the first and second joint elements, a welding portion prepared at an end of the projection is welded on a surface thereof in contact with the recess. 
     
     
         16 . The method of  claim 10 , wherein the welding of the first and second joint elements is performed by ultrasonic welding. 
     
     
         17 . The method of  claim 10 , wherein the first portion of the first and second external terminals is exposed to the same outer surface of the lower case, and
 the same outer surface is provided as a mounting surface for the chip-type electric double layer capacitor.   
     
     
         18 . The method of  claim 17 , wherein the second portion of the first and second external terminals extends to side surfaces connected to the mounting surface. 
     
     
         19 . The method of  claim 10 , wherein the electrical connecting of the electric double layer capacitor cell is performed by welding or ultrasonic welding. 
     
     
         20 . A chip-type electric double layer capacitor comprising:
 a resin case having a housing space provided therein and formed of insulating resin;   first and second external terminals inserted into the resin case by insert injection molding, each having a first portion exposed to an outer surface of the resin case for external contact and a second portion exposed to an inner surface of the housing space for internal contact;   a sealing portion including a groove portion provided in the resin case along a circumference of at least one of the first and second external terminals and a resin filling the groove portion; and   an electric double layer capacitor cell mounted in the housing space and electrically connected to the second portion of the first and second external terminals.   
     
     
         21 . The chip-type electric double layer capacitor of  claim 20 , wherein the sealing portion is provided to both the first and second external terminals individually. 
     
     
         22 . The chip-type electric double layer capacitor of  claim 21 , wherein the sealing portion is provided to enclose the circumference of the first and second external terminals. 
     
     
         23 . The chip-type electric double layer capacitor of  claim 21 , wherein the sealing portion is provided in part of the circumference of the first and second external terminals. 
     
     
         24 . The chip-type electric double layer capacitor of  claim 23 , wherein the groove portion is provided in the inner surface of the housing space along a circumference of the second portion of the first and second external terminals. 
     
     
         25 . The chip-type electric double layer capacitor of  claim 23 , wherein the groove portion is provided in the outer surface of the resin case along a circumference of the first portion of the first and second external terminals. 
     
     
         26 . The chip-type electric double layer capacitor of  claim 20 , wherein the first portion of the first and second external terminals is exposed to the same outer surface of the resin case, and
 the same outer surface is provided as a mounting surface for the chip-type electric double layer capacitor.   
     
     
         27 . The chip-type electric double layer capacitor of  claim 20 , wherein the second portion of the first and second external terminals extends to side surfaces connected to the mounting surface. 
     
     
         28 . The chip-type electric double layer capacitor of  claim 20 , wherein the resin case comprises:
 a lower case having a housing space of which a top surface is opened and formed together with the first and second external terminals by insert injection molding; and   an upper cap mounted on the lower case so as to cover the housing space.   
     
     
         29 . The chip-type electric double layer capacitor of  claim 28 , wherein the upper cap is mounted on the lower case by using an adhesive. 
     
     
         30 . The chip-type electric double layer capacitor of  claim 20 , wherein the electric double layer capacitor cell is electrically connected to the second portion of the first and second external terminals by welding or ultrasonic welding.