Multilayered box in fdsoi mosfets

Abstract

A fully depleted MOSFET has a semiconductor-on-insulator substrate that includes a substrate material, a BOX positioned on the substrate material, and an active layer positioned on the BOX. The BOX includes a first layer of material with a first dielectric constant and a first thickness and a second layer of material having a second dielectric constant different than the first dielectric constant and a second thickness different than the first thickness. The first layer of material is positioned adjacent the substrate material and the second layer of material is positioned adjacent the active layer. Drain and source regions are formed in the active layer so as to be fully depleted. The drain and source regions are separated by a channel region in the active layer. A gate insulating layer overlies the channel region and a gate stack is positioned on the gate insulating region. It is anticipated that the structure is most useful for channel regions less than 90 nm long.

1 - 21 . (canceled) 
     
     
         22 . A method of manufacturing a short channel fully depleted device on an SOI structure, the method increasing performance and alleviating manufacturing tolerances and including the steps of:
 providing a substrate;   forming a BOX in the substrate with an active layer on the BOX, the device having a subthreshold slope and the BOX having an associated drain-induced-barrier-lowering effect; and   adjusting the dielectric constant of at least a portion of the BOX to be lower than the dielectric constant of SiO 2  so as to reduce the subthreshold slope and the drain-induced-barrier-lowering effect associated with the BOX.   
     
     
         23 . A method as claimed in  claim 22  wherein the step of forming the BOX in the substrate and the active layer includes epitaxially fabricating the device. 
     
     
         24 . A method as claimed in  claim 22  wherein the step of forming the BOX in the substrate and the active layer includes a wafer bonding technique. 
     
     
         25 . A method as claimed in claim in  claim 22  further including a step of forming the BOX with more than one layer and the step of adjusting the dielectric constant includes adjusting the dielectric constant of one layer of the more than one layers. 
     
     
         26 . A method as claimed in claim in  claim 25  wherein the of step of forming the BOX with more than one layer and the step of adjusting the dielectric constant includes adjusting the dielectric constant of one layer of the more than one layers immediately adjacent the active layer. 
     
     
         27 . An SOI structure comprising:
 a semiconductor-on-insulator substrate including substrate material, a BOX positioned on the substrate material, and an active layer positioned on the BOX; and   the BOX including a first layer of material with a first dielectric constant and a first thickness and a second layer of material having a second dielectric constant different than the first dielectric constant and a second thickness different than the first thickness, the first layer of material being positioned adjacent the substrate material and the second layer of material being positioned adjacent the active layer, the dielectric constant of at least a portion of the BOX being lower than the dielectric constant of SiO 2  so as to reduce a drain-induced-barrier-lowering effect associated with the BOX.   
     
     
         28 . An SOI structure as claimed in  claim 27  wherein the first dielectric constant is higher than the second dielectric constant. 
     
     
         29 . An SOI structure as claimed in  claim 28  wherein the first dielectric constant is higher than the dielectric constant of SiO 2  and the second dielectric constant is lower than the dielectric constant of SiO 2 . 
     
     
         30 . An SOI structure as claimed in  claim 28  wherein the thickness of the first layer of material is greater than the thickness of the second layer of material. 
     
     
         31 . An SOI structure as claimed in  claim 27  wherein the BOX includes a third layer of material. 
     
     
         32 . An SOI structure as claimed in  claim 27  wherein the substrate material includes single crystal material. 
     
     
         33 . An SOI structure as claimed in  claim 32  wherein the single crystal material includes silicon. 
     
     
         34 . An SOI structure as claimed in  claim 27  wherein the active layer includes single crystal material. 
     
     
         35 . A short channel fully depleted device on an SOI structure comprising:
 a semiconductor-on-insulator substrate including substrate material;   a BOX in the substrate with an active layer on the BOX, the device having a subthreshold slope; and   the BOX including a first layer of material with a first dielectric constant and a first thickness and a second layer of material having a second dielectric constant different than the first dielectric constant and a second thickness different than the first thickness, the first layer of material being positioned adjacent the substrate material and the second layer of material being positioned adjacent the active layer, the dielectric constant of at least a portion of the BOX being lower than the dielectric constant of SiO 2  so as to reduce the subthreshold slope and a drain-induced-barrier-lowering effect associated with the BOX.