Pll circuit

Abstract

A PLL comprises a current-controlled oscillator ( 18 ) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source ( 28 ), and an initialization switch ( 26 ) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator ( 18 ) and the current source ( 28 ).

1 - 16 . (canceled) 
     
     
         17 . A PLL circuit comprising:
 a phase detector for comparing a phase difference between a reference clock signal and a feedback clock signal;   a loop filter for smoothing a current which is pushed and pulled in accordance with a result of phase comparison by the phase detector;   a voltage-current converting circuit for converting an output voltage of the loop filter into a current;   a clock generating circuit for generating a dummy clock signal having a phase difference with reference to the reference clock signal;   a selector for inputting the dummy clock signal to the phase detector when an initialization signal is at a predetermined logic level, and the feedback clock signal to the phase detector when the initialization signal is at a logic level other than the predetermined logic level;   a reset switch which, when receiving a reset signal, goes to a conductive state, and otherwise, goes to a non-conductive state, the reset switch being provided between an input terminal of the voltage-current converting circuit and a ground node;   a deadlock detecting circuit for detecting that the PLL circuit is in a deadlock state; and   a control section for outputting the reset signal when the deadlock state detected by the deadlock detecting circuit continues for a predetermined time or more, and outputting the initialization signal having the predetermined logic level during start-up of the PLL circuit and following the outputting of the reset signal.   
     
     
         18 . The PLL circuit of  claim 17 , wherein the clock generating circuit comprises:
 an inverter for inverting the reference clock; and   a divider for generating the dummy clock signal from an output of the inverter.   
     
     
         19 . The PLL circuit of  claim 17 , further comprising:
 a fractional-N frequency divider for generating the feedback clock signal from the output clock signal; and   a ΔΣ controller for supplying a fractional-N frequency division ratio to the fractional-N frequency divider.   
     
     
         20 . The PLL circuit of  claim 19 , wherein the ΔΣ controller, when receiving the initialization signal, supplies a predetermined integer frequency-division ratio to the fractional-N frequency divider based on the initialization signal. 
     
     
         21 . A PLL circuit comprising:
 a phase detector for comparing a phase difference between a reference clock signal and a feedback clock signal;   a clock generating circuit for generating a dummy clock signal having a phase difference with reference to the reference clock signal; and   a selector for selectively inputting the feedback clock signal or the dummy clock signal to the phase detector based on an initialization signal during start-up of the PLL circuit.   
     
     
         22 . The PLL circuit of  claim 21 , wherein the clock generating circuit comprises:
 an inverter for inverting the reference clock; and   a divider for generating the dummy clock signal from an output of the inverter.   
     
     
         23 . The PLL circuit of  claim 21 , further comprising:
 a fractional-N frequency divider for generating the feedback clock signal from the output clock signal; and   a ΔΣ controller for supplying a fractional-N frequency division ratio to the fractional-N frequency divider.   
     
     
         24 . The PLL circuit of  claim 23 , wherein the ΔΣ controller supplies a predetermined integer frequency-division ratio to the fractional-N frequency divider based on the initialization signal.