Non-volatile electrically alterable memory cell for storing multiple data

Abstract

A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.

1 . An electrically alterable memory device, comprising:
 (a) a semiconductor substrate having a surface, comprising:
 a first semiconductor layer of a first conductivity type at the surface of the semiconductor substrate, the first semiconductor layer having a first dopant concentration; and 
 a first diffusion region and a second diffusion region also provided at the surface of the semiconductor substrate spaced apart by a portion of the first semiconductor layer, thereby forming a channel region in the first semiconductor layer between the diffusion regions, each diffusion region being of a second conductivity type opposite to the first conductivity type and each diffusion region having a second dopant concentration greater than the first dopant concentration such that the first semiconductor layer and each diffusion region form a junction which breaks down according to a soft avalanche breakdown mechanism; 
   (b) a gate dielectric layer provided over the surface of the semiconductor substrate;   (c) a first floating gate and a second floating gate each comprising a conductive material, the floating gates respectively disposed at least in part overlapping the junctions, separated therefrom by the gate dielectric layer; and   (d) a control gate also comprising a conductive material, the control gate being disposed laterally between the first floating gate and the second floating gate and separated from each floating gate by an insulator layer having a thickness such that, when an electrical potential is imposed on the control gate, a portion of the electrical potential is capacitively coupled to the floating gates, and wherein the gate dielectric layer is of a thickness such that, when a soft avalanche break down occurs in a junction, electrical charge is injected by the capacitively coupled electrical potential into the corresponding overlapping floating gate.   
     
     
         2 . The memory device of  claim 1 , wherein the gate dielectric layer allows tunneling of electrical charge between one of the floating gates and the channel region. 
     
     
         3 . The memory device of  claim 1 , wherein the gate dielectric layer is between 70 Angstroms and 110 Angstroms thick. 
     
     
         4 . The memory device of  claim 1 , wherein the insulator layer comprises a silicon dioxide having a thickness that is sufficiently thick to prevent current leakage between the control gate and each of the floating gates. 
     
     
         5 . The memory device of  claim 1 , wherein the insulator layer comprises an oxide-nitride-oxide layer. 
     
     
         6 . The memory device of  claim 1 , wherein each floating gate stores a predetermined amount of electrical charge controlled by the capacitively coupled electrical potential. 
     
     
         7 . The memory device of  claim 1 , further comprising contacts to the first diffusion region and the second diffusion region, each contact being selectably coupled to a reference voltage or a variable voltage, so as to allow independent charging and discharging of the first floating gate and the second floating gate. 
     
     
         8 . The memory device of  claim 1 , wherein the first and second diffusion regions are defined by a self-aligned process using the first and second floating gates, respectively. 
     
     
         9 . The memory device of  claim 1 , wherein the first diffusion region and the second diffusion region are P-type. 
     
     
         10 . The memory device of  claim 9  wherein, when the soft avalanche breakdown mechanism occurs, the channel region is rendered non-conducting.