US2011128274A1PendingUtilityA1

Integrated Circuit Device and Electronic Instrument

44
Assignee: SEIKO EPSON CORPPriority: Jun 30, 2005Filed: Feb 8, 2011Published: Jun 2, 2011
Est. expiryJun 30, 2025(expired)· nominal 20-yr term from priority
H10D 89/10G09G 3/3688G02F 1/133G02F 1/1345G09G 3/20G09G 3/36H10B 10/18H10B 10/00
44
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Claims

Abstract

An integrated circuit device includes first and second transistors NTr 1 and PTr 1 push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTr 1 and PTr 1 so that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTr 1 and PTr 1.

Claims

exact text as granted — not AI-modified
1 . A driver that drives a display panel, the driver comprising:
 a first power supply line;   a second power supply line;   a first transistor;   a second transistor, the first transistor and the second transistor being push-pull connected to a connection node between the first power supply line and the second power supply line, the first transistor and the second transistor outputting a voltage of one of the first power supply line and the second power supply line to the connection node by a charge-pump operation using a flying capacitor; and   a pad electrically connected with the connection node and electrically connected with the flying capacitor,   the pad being disposed in an upper layer of at least one of the first transistor and the second transistor so that the pad overlaps a part or an entirety of at least one of the first transistor and the second transistor,   at least one of the first transistor and the second transistor having a drain region, a contact being disposed between the drain region and the first pad,   the drain region and the contact being disposed in a lower layer of the pad so that the pad overlaps a part or an entirety of the drain region and the contact.   
     
     
         2 . The driver as defined in  claim 1 , comprising:
 a power supply circuit that generates a power supply,   
     
     
         3 . The driver as defined in  claim 2 ,
 the power supply circuit including a VCOM generation circuit that generates a voltage VCOM supplied to a common electrode of the display panel.   
     
     
         4 . The driver as defined in  claim 3 ,
 the power supply circuit generates the voltage VCOM based on a boost voltage generated by the first transistor and the second transistor.   
     
     
         5 . The driver as defined in  claim 2 ,
 the power supply circuit including a boost clock signal generation section that generates boost clock signals that gate-control the first transistor and the second transistor.   
     
     
         6 . The driver as defined in  claim 1 , comprising:
 a grayscale voltage generation circuit that generates grayscale voltages.   
     
     
         7 . The driver as defined in  claim 6 ,
 the grayscale voltage generation circuit generating the grayscale voltages based on a boost voltage generated by the first transistor and the second transistor.   
     
     
         8 . The driver as defined in  claim 1 , comprising:
 an electrostatic discharge protection, one end of the electrostatic discharge protection being connected to the connection node of the first transistor and the second transistor,   the pad being disposed in an upper layer of at least one of the electrostatic discharge protection element, the first transistor and the second transistor so that the pad overlaps a part or an entirety of at least one of the electrostatic discharge protection element, the first transistor and the second transistor.   
     
     
         9 . The driver as defined in  claim 1 , comprising:
 a first interface region in which the pad is disposed,   the first transistor and the second transistor being disposed in the first interface region.   
     
     
         10 . The driver as defined in  claim 9 , comprising:
 a second interface region that serves as an interface between the driver and the display panel.   
     
     
         11 . The driver as defined in  claim 10 , comprising:
 first to Nth circuit blocks (N is an integer of two or more) disposed along a first direction, the first direction being a direction from a first side which is a short side of the driver toward a third side opposite to the first side,   the first to Nth circuit blocks disposed between the first interface region and the second interface region.   
     
     
         12 . The driver as defined in  claim 11 ,
 the first to Nth circuit blocks including a logic circuit block that generates control signals of the driver.   
     
     
         13 . The driver as defined in  claim 11 ,
 the first to Nth circuit blocks including memory blocks that store image data of the display panel.   
     
     
         14 . The driver as defined in  claim 13 ,
 the memory blocks including a first memory block and a second memory block,   the first memory block and the second memory block being adjacently disposed along the first direction.   
     
     
         15 . The driver as defined in  claim 11 ,
 when widths of the first interface region, the first to Nth circuit blocks, and the second interface region in a second direction perpendicular to the first direction are respectively W 1 , WB, and W 2 , the driver having a width W in the second direction of “W 1 +WB+W 2 ≦W<W 1 +2×WB+W 2 ”.   
     
     
         16 . The driver as defined in  claim 15 ,
 the width W of the driver in the second direction being “W<2×WB”.   
     
     
         17 . An electronic instrument comprising:
 the driver as defined in  claim 1 ; and   the display panel driven by the driver.

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