Through substrate annular via including plug filler

Abstract

A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.

1 . A method for fabricating a microelectronic structure comprising:
 forming a blind aperture within a substrate;   successive layering and subsequently planarizing within the blind aperture a conformal conductor layer that does not completely fill the blind aperture and a plug layer that does completely fill the aperture; and   planarizing a backside of the substrate to expose at least the conformal conductor layer.   
     
     
         2 . The method of  claim 1  wherein the forming the blind aperture provides the blind aperture with a linewidth from about 5 to about 15 microns and an aspect ratio from about 1:10 to about 1:30. 
     
     
         3 . The method of  claim 1  wherein the successive layering further comprises successive layering a conformal liner layer into the aperture prior to the successive layering of the conformal conductor layer. 
     
     
         4 . The method of  claim 1  wherein the successive layering further comprises successive layering a conformal stop layer after successive layering the conformal conductor layer and prior to successive layering the plug layer. 
     
     
         5 . The method of  claim 1  wherein the planarizing the backside exposes only the conformal conductor layer. 
     
     
         6 . The method of  claim 1  wherein the planarizing the backside exposes the conformal conductor layer and the plug layer. 
     
     
         7 . The method of claim  14  further comprising forming a conductor layer over the substrate and contacting the planarized conformal conductor layer. 
     
     
         8 . The method of  claim 1  further comprising forming a conductor layer under the substrate and contacting the planarized conformal conductor layer. 
     
     
         9 . A method for fabricating a microelectronic structure comprising:
 forming a blind aperture within a semiconductor substrate;   successive layering and subsequently planarizing within the blind aperture a conformal dielectric liner layer that does not completely fill the aperture, a conformal conductor layer that does not completely fill the blind aperture, a conformal stop layer that does not completely fill the aperture and a plug layer that does completely fill the aperture; and   planarizing a backside of the substrate to expose at least the conformal conductor layer.   
     
     
         10 . The method of  claim 9  wherein the forming the blind aperture provides the blind aperture with a linewidth from about 5 to about 15 microns and an aspect ratio from about 10:1 to about 30:1. 
     
     
         11 . The method of  claim 9  wherein the planarizing the backside exposes the conformal conductor layer but not the plug layer. 
     
     
         12 . The method of  claim 9  wherein the planarizing the backside exposes the conformal conductor layer and the plug layer.