Hashing packet contents to determine a processor

Abstract

The disclosure includes a description of an apparatus having circuitry to determine a first hash value for a first packet tuple of a first packet traveling in a first direction of a duplex connection and determine a processor for the first packet from a set of multiple processors based, at least in part, on the first hash value. The apparatus includes circuitry to determine a second hash value for a second packet tuple of a second packet traveling in a second direction of the duplex connection and determine the same processor for the second packet from the set of multiple processors based, at least in part, on the second hash value.

1 - 15 . (canceled) 
     
     
         16 . A method, comprising:
 for a first packet received at a network interface of a system comprising multiple processors:
 ordering the Internet Protocol source address and the Internet Protocol destination address of the first packet by magnitude and ordering the source port and destination port of the first packet by magnitude; 
 performing a hash based, at least in part, on the ordering of the Internet Protocol source address and the Internet Protocol destination address of the first packet by magnitude and the ordering of the source port and destination port of the first packet by magnitude; and 
 determining a processor from the multiple processors based on the performed hash. 
   
     
     
         17 . The method of  claim 16 , further comprising:
 for a second packet to be transmitted via the network interface to a remote destination:
 ordering the Internet Protocol source address and the Internet Protocol destination address of the second packet by magnitude and ordering the source port and destination port of the second packet by magnitude; 
 performing a hash based, at least in part, on the ordering of the Internet Protocol source address and the Internet Protocol destination address of the second packet by magnitude and the ordering of the source port and destination port of the second packet by magnitude. 
   
     
     
         18 . The method of  claim 16 , wherein the determining the processor comprises using the performed hash to perform a lookup associating hash values with indications of processors. 
     
     
         19 . The method of  claim 16 , wherein the hash comprises a Toeplitz hash. 
     
     
         20 . The method of  claim 16 , wherein the determining the processor comprises selecting a queue associated with the processor. 
     
     
         21 . A computer program, disposed on a non-transitory computer readable medium, comprising instructions to cause circuitry to:
 for a received packet:
 order the Internet Protocol source address and the Internet Protocol destination address of the first received packet by magnitude and order the source port and destination port of the first received packet by magnitude; 
 performing a hash, based at least in part, on the ordering of the Internet Protocol source address and the Internet Protocol destination address of the received packet by magnitude and the ordering of the source port and destination port of the first received packet by magnitude; and 
 determine a processor from a set of multiple processors based on the performed hash. 
   
     
     
         22 . The computer program of  claim 21 , further comprising instructions for causing circuitry to:
 for a second packet to be transmitted via the network interface to a remote destination:
 order the Internet Protocol source address and the Internet Protocol destination address of the second packet by magnitude and order the source port and destination port of the second packet by magnitude; 
 perform a hash, based at least in part, on the ordering of the Internet Protocol source address and the Internet Protocol destination address of the second packet by magnitude and the order of the source port and destination port of the second packet by magnitude. 
   
     
     
         23 . The computer program of  claim 21 , wherein the instructions to determine the processor comprise instructions to use the performed hash to perform a lookup associating hash values with indications of processors. 
     
     
         24 . The computer program of  claim 21 , wherein the hash comprises a Toeplitz hash. 
     
     
         25 . The computer program of  claim 21 , wherein the determining the processor comprises selecting a queue associated with the processor. 
     
     
         26 . A system, comprising
 multiple processors;   at least one network interface controller coupled to the multiple processors; and   circuitry to:
 for a received packet:
 order the Internet Protocol source address and the Internet Protocol destination address of the received packet by magnitude and order the source port and destination port of the receive packet by magnitude; 
 perform a hash based, at least in part, on the ordering of the Internet Protocol source address and the Internet Protocol destination address of the received packet by magnitude and on the ordering of the source port and destination port of the received packet by magnitude; and 
 determine a processor from the multiple processors based on the performed hash. 
 
   
     
     
         27 . The system of  claim 26 , wherein the circuitry comprises circuitry to:
 for a second packet to be transmitted via the network interface to a remote destination:
 order the Internet Protocol source address and the Internet Protocol destination address of the second packet by magnitude and order the source port and destination port of the second packet by magnitude; and 
 perform a hash, based at least in part, on the ordering of the Internet Protocol source address and the Internet Protocol destination address of the second packet by magnitude and the ordering of the source port and destination port by magnitude. 
   
     
     
         28 . The system of  claim 26 , wherein the circuitry to determine the processor comprises circuitry to use the performed hash to perform a lookup associating hash values with indications of processors. 
     
     
         29 . The system of  claim 26 , wherein the hash comprises a Toeplitz hash. 
     
     
         30 . The system of  claim 26 , wherein the circuitry to determine the processor comprises circuitry to select a queue associated with the processor. 
     
     
         31 . The system of  claim 26 , wherein the circuitry comprises circuitry programmed by instructions disposed on a non-transitory computer readable medium.